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authorElyes HAOUAS <ehaouas@noos.fr>2020-04-22 16:49:28 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-04-23 22:21:11 +0000
commita4faec3b014b54d4619dad31c6d6ede58700d862 (patch)
treedc39875d437a0f357d1e142644d1108b83138ce2 /src/mainboard/google/jecht
parentcfdac8266155e7aafdc658e415eb719639670ed8 (diff)
downloadcoreboot-a4faec3b014b54d4619dad31c6d6ede58700d862.tar.xz
src/mainboard: Const'ify pci_devfn_t devices
Change-Id: I5bb1a819475383719dbda32d9b5fea63da1e6713 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/google/jecht')
-rw-r--r--src/mainboard/google/jecht/chromeos.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c
index b58b35a31f..90284c564f 100644
--- a/src/mainboard/google/jecht/chromeos.c
+++ b/src/mainboard/google/jecht/chromeos.c
@@ -30,20 +30,20 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_write_protect_state(void)
{
- pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
+ const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
}
int get_recovery_mode_switch(void)
{
- pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
+ const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;
}
void init_bootmode_straps(void)
{
u32 flags = 0;
- pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
+ const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
/* Write Protect: GPIO58 = GPIO_SPI_WP, active high */
if (get_gpio(GPIO_SPI_WP))