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author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-07-25 11:12:15 -0600 |
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committer | Martin Roth <martinroth@google.com> | 2017-07-27 21:33:09 +0000 |
commit | 6b75ee2220d66815f7f4f2ce32f04b74ded9685f (patch) | |
tree | fcc312dec9c383901a95f6439b446bf1cf008d0a /src/mainboard/google/kahlee/BiosCallOuts.c | |
parent | b925f8bce61ba938e5839bd285329bc704f3373a (diff) | |
download | coreboot-6b75ee2220d66815f7f4f2ce32f04b74ded9685f.tar.xz |
google/kahlee: Update PCIe link/lane configuration
Enable:
GPP0 x1 - WLan
GPP1 x1 - Card Reader
Change-Id: Idbfc2a3260b85949810bdd8dc904e59f8a779e48
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/kahlee/BiosCallOuts.c')
0 files changed, 0 insertions, 0 deletions