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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-07-25 18:55:44 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-07-27 21:33:16 +0000 |
| commit | 5f339163b09a8d4be4d82bfe4921edef33425303 (patch) | |
| tree | 6f84199d2d5cc19d8a2deb54e0394816246285a2 /src/mainboard/google/kahlee/Makefile.inc | |
| parent | 6b75ee2220d66815f7f4f2ce32f04b74ded9685f (diff) | |
| download | coreboot-5f339163b09a8d4be4d82bfe4921edef33425303.tar.xz | |
google/kahlee: Pass GPIO setting in amdinitenv
GPIOs for I2C3 were being unset in amdinitmid if the GPIO
enable table wasn't passed. It had been initialy set in amdinitreset.
Pull the GPIO settings into their own file that can be used in
bootblock and later stages.
Change-Id: I41cd7873f8c8543c95ad8653e0a3887f7d0487a2
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/kahlee/Makefile.inc')
| -rw-r--r-- | src/mainboard/google/kahlee/Makefile.inc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/kahlee/Makefile.inc b/src/mainboard/google/kahlee/Makefile.inc index 665e086dc7..6db037f726 100644 --- a/src/mainboard/google/kahlee/Makefile.inc +++ b/src/mainboard/google/kahlee/Makefile.inc @@ -17,14 +17,17 @@ bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/BiosCallOuts.c bootblock-y += bootblock/OemCustomize.c bootblock-y += ec.c +bootblock-y += gpio.c romstage-y += BiosCallOuts.c romstage-y += chromeos.c +romstage-y += gpio.c romstage-y += OemCustomize.c ramstage-y += BiosCallOuts.c ramstage-y += chromeos.c ramstage-y += ec.c +ramstage-y += gpio.c ramstage-y += OemCustomize.c verstage-y += chromeos.c |