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| author | Marc Jones <marcj303@gmail.com> | 2017-05-22 21:35:16 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-07-27 21:31:32 +0000 |
| commit | 2d79f16dc81037620ead4e3b49eb470726aec3f2 (patch) | |
| tree | b19cf32c5c2ac9d7104231953cb76ba71f8d981d /src/mainboard/google/kahlee/acpi/mainboard.asl | |
| parent | b14e04bd7c492a551532dc3678a1cc922b3cedf8 (diff) | |
| download | coreboot-2d79f16dc81037620ead4e3b49eb470726aec3f2.tar.xz | |
google/kahlee: Start Kahlee mainboard
Copied from amd/gardenia. Update the appropriate board name strings.
Uses the soc/ structure.
Change-Id: Ia68b16969518f4d63d5d2dea7658a472b2daca05
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/kahlee/acpi/mainboard.asl')
| -rw-r--r-- | src/mainboard/google/kahlee/acpi/mainboard.asl | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/src/mainboard/google/kahlee/acpi/mainboard.asl b/src/mainboard/google/kahlee/acpi/mainboard.asl new file mode 100644 index 0000000000..508daa7234 --- /dev/null +++ b/src/mainboard/google/kahlee/acpi/mainboard.asl @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Memory related values */ +Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ +Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ +Name(PBLN, 0x0) /* Length of BIOS area */ + +Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ +Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ +Name(HPBA, 0xFED00000) /* Base address of HPET table */ + +Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + +/* Some global data */ +Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ +Name(OSV, Ones) /* Assume nothing */ +Name(PMOD, One) /* Assume APIC */ |