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| author | Richard Spiegel <richard.spiegel@amd.corp-partner.google.com> | 2018-04-20 16:50:12 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-05-27 01:03:28 +0000 |
| commit | 2db06bba0fdeb2465108da487b0b2d1ecedef985 (patch) | |
| tree | 49591ccccf5f171fd4e984cd517615ec8886b748 /src/mainboard/google/kahlee/bootblock | |
| parent | 2aa13eff9d5df7c19898acecbcdb2fda1ec00d44 (diff) | |
| download | coreboot-2db06bba0fdeb2465108da487b0b2d1ecedef985.tar.xz | |
stoneyridge GPIO: Create and use PAD_INT for interrupt pins
The default interrupt control for GPIO pins within stoneyridge is for
edge triggered, high. However, sometimes these need to change, or maybe
the interrupt needs to be reported or delivered. This was the case of
platform grunt, where the interrupt related bits were being changed
afterwards. Ideally all the bits should be programmed through the same
procedure. Create several PAD_INT definitions (for general configuration,
for trigger configuration and for interrupt type configuration) and change
function sb_program_gpios() to accept the output from PAD_INT_XX and
program all the necessary bits while keeping compatibility with other
PAD_XX definitions.
BUG=b:72875858
TEST=Add code to report GPIO and interrupt configuration, build grunt and
record a baseline. Add new code, rebuild grunt and record a test output.
Compare baseline against test, there should be no change in GPIO or
interrupt programming.
Remove code that reports GPIO/interrupt configuration.
Change-Id: I3457543bdf64ec757fd82df53c83fdc1d03c1f22
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/kahlee/bootblock')
| -rw-r--r-- | src/mainboard/google/kahlee/bootblock/bootblock.c | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c index aac1d955d9..8f124b36ff 100644 --- a/src/mainboard/google/kahlee/bootblock/bootblock.c +++ b/src/mainboard/google/kahlee/bootblock/bootblock.c @@ -50,11 +50,4 @@ void bootblock_mainboard_init(void) /* Setup TPM decode before verstage */ sb_tpm_decode_spi(); - - /* Configure cr50 interrupt pin for use in polling tpm status */ - if (IS_ENABLED(CONFIG_MAINBOARD_HAS_TPM_CR50)) { - const uint32_t flags = GPIO_EDGE_TRIG | GPIO_ACTIVE_LOW | - GPIO_INT_STATUS_EN; - gpio_set_interrupt(H1_PCH_INT, flags); - } } |