diff options
| author | Chris Ching <chingcodes@google.com> | 2018-02-06 10:28:49 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2018-02-21 23:36:22 +0000 |
| commit | 97ab880082505b4aa0d4b2a058e850bd3376d9b8 (patch) | |
| tree | d099da762a2be578eac58592fdbc1ee5e49e413d /src/mainboard/google/kahlee/bootblock | |
| parent | 2269a3c328c335aa57d7094ca24a9d21ee6ade7d (diff) | |
| download | coreboot-97ab880082505b4aa0d4b2a058e850bd3376d9b8.tar.xz | |
mainboard/google/kahlee: Add tis_plat_irq_status
For variants that have a cr50 tpm, this enables faster polling when
interacting with the tpm.
BUG=b:72838769
BRANCH=none
TEST=verified on grunt that irq is used and not timeouts for tpm
Change-Id: I5786d334b6c1cc70f4c7107c75b07a7e27ac4428
Signed-off-by: Chris Ching <chingcodes@chromium.org>
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/kahlee/bootblock')
| -rw-r--r-- | src/mainboard/google/kahlee/bootblock/bootblock.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c index 244abe051f..4a65d8f4fc 100644 --- a/src/mainboard/google/kahlee/bootblock/bootblock.c +++ b/src/mainboard/google/kahlee/bootblock/bootblock.c @@ -15,8 +15,10 @@ #include <baseboard/variants.h> #include <bootblock_common.h> +#include <soc/gpio.h> #include <soc/southbridge.h> #include <variant/ec.h> +#include <variant/gpio.h> void bootblock_mainboard_init(void) { @@ -30,4 +32,11 @@ void bootblock_mainboard_init(void) /* Setup TPM decode before verstage */ sb_tpm_decode_spi(); + + /* Configure cr50 interrupt pin for use in polling tpm status */ + if (IS_ENABLED(CONFIG_MAINBOARD_HAS_TPM_CR50)) { + const uint32_t flags = GPIO_EDGEL_TRIG | GPIO_ACTIVE_LOW | + GPIO_INT_STATUS_EN; + gpio_set_interrupt(H1_PCH_INT, flags); + } } |