diff options
| author | Simon Glass <sjg@chromium.org> | 2018-07-12 14:20:21 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-07-16 07:41:51 +0000 |
| commit | acad6212c8caf94edf84675537e78dd170edf2f4 (patch) | |
| tree | d740ba9cdc041deeac700130baaa9a81246783f2 /src/mainboard/google/kahlee/bootblock | |
| parent | 46255f7ee4728e0ee02c0cb8d9edeeee1a8e5361 (diff) | |
| download | coreboot-acad6212c8caf94edf84675537e78dd170edf2f4.tar.xz | |
mainboard/google/kahlee: Add support for Dediprog em100
This device claims to run at 75MHz with dual read, but it is not always
reliable. Add an option to change the SPI flash speed to 16MHz, to avoid
any problems.
BUG=b:111363976
TEST=manually try to get my em100 running (it doesn't yet)
Change-Id: I78d3d32c467aac82c72d31c773bfb0f69808aed4
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/27466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/kahlee/bootblock')
| -rw-r--r-- | src/mainboard/google/kahlee/bootblock/bootblock.c | 36 |
1 files changed, 24 insertions, 12 deletions
diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c index 7e6524d1d5..8531fc0de2 100644 --- a/src/mainboard/google/kahlee/bootblock/bootblock.c +++ b/src/mainboard/google/kahlee/bootblock/bootblock.c @@ -34,19 +34,31 @@ void bootblock_mainboard_early_init(void) void bootblock_mainboard_init(void) { - /* - * W25Q128FW Setup - * Normal Read 40MHz - * Fast Read 104MHz - * Dual Read IO (1-2-2) - */ - sb_read_mode(SPI_READ_MODE_DUAL122); + if (IS_ENABLED(CONFIG_EM100)) { + /* + * We should be able to rely on defaults, but it seems safer + * to explicitly set up these registers. + */ + sb_read_mode(SPI_READ_MODE_NOM); + sb_set_spi100(SPI_SPEED_16M, /* Normal */ + SPI_SPEED_16M, /* Fast */ + SPI_SPEED_16M, /* AltIO */ + SPI_SPEED_66M); /* TPM */ + } else { + /* + * W25Q128FW Setup + * Normal Read 40MHz + * Fast Read 104MHz + * Dual Read IO (1-2-2) + */ + sb_read_mode(SPI_READ_MODE_DUAL122); - /* Set SPI speeds before verstage. Needed for TPM */ - sb_set_spi100(SPI_SPEED_33M, /* Normal */ - SPI_SPEED_66M, /* Fast */ - SPI_SPEED_66M, /* AltIO */ - SPI_SPEED_66M); /* TPM */ + /* Set SPI speeds before verstage. Needed for TPM */ + sb_set_spi100(SPI_SPEED_33M, /* Normal */ + SPI_SPEED_66M, /* Fast */ + SPI_SPEED_66M, /* AltIO */ + SPI_SPEED_66M); /* TPM */ + } /* Setup TPM decode before verstage */ sb_tpm_decode_spi(); |