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authorJonathan Neuschäfer <j.neuschaefer@gmx.net>2018-04-08 15:05:12 +0200
committerMartin Roth <martinroth@google.com>2018-04-11 14:18:35 +0000
commit73cd7cf0f28d77a9a4afe56ca0e0a9485b2eae48 (patch)
tree663da369409a6ef89d480f6ca99846862ab96c07 /src/mainboard/google/kahlee/bootblock
parentf42c7d9670302bac9119f0473e4283882960ffbb (diff)
downloadcoreboot-73cd7cf0f28d77a9a4afe56ca0e0a9485b2eae48.tar.xz
src/amd/stoneyridge: Fix a typo (EDGEL_TRIG -> EDGE_TRIG)
Fixes: 2269a3c328 ("soc/amd/stoneyridge: Add functions for GPIO interrupts") Change-Id: I5730259bc6819defc482d31644e1f476679257b2 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25588 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Chris Ching <chingcodes@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/kahlee/bootblock')
-rw-r--r--src/mainboard/google/kahlee/bootblock/bootblock.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c
index 1eb18f1667..641287c1bd 100644
--- a/src/mainboard/google/kahlee/bootblock/bootblock.c
+++ b/src/mainboard/google/kahlee/bootblock/bootblock.c
@@ -39,7 +39,7 @@ void bootblock_mainboard_init(void)
/* Configure cr50 interrupt pin for use in polling tpm status */
if (IS_ENABLED(CONFIG_MAINBOARD_HAS_TPM_CR50)) {
- const uint32_t flags = GPIO_EDGEL_TRIG | GPIO_ACTIVE_LOW |
+ const uint32_t flags = GPIO_EDGE_TRIG | GPIO_ACTIVE_LOW |
GPIO_INT_STATUS_EN;
gpio_set_interrupt(H1_PCH_INT, flags);
}