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authorMarc Jones <marcj303@gmail.com>2017-04-18 18:02:23 -0600
committerMartin Roth <martinroth@google.com>2017-07-31 17:18:13 +0000
commit42e20643700aee9039a605e98e4a1339ab42619c (patch)
treefc8711d25c7284b5ed8f86ca0a721ab409067631 /src/mainboard/google/kahlee/cmos.layout
parent965f5e2d53932ee9c080dabb63bdb243f43eadcc (diff)
downloadcoreboot-42e20643700aee9039a605e98e4a1339ab42619c.tar.xz
google/kahlee: Save VBNV data to CMOS
Store VBOOT NV data in CMOS. This allows VBOOT to save flags and data to be used in multiple stages and depthcharge. Fixes developer mode USB boot. Change-Id: I50b45e687a1a1c71838bcc390212b28d7e634a19 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/kahlee/cmos.layout')
-rw-r--r--src/mainboard/google/kahlee/cmos.layout2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/kahlee/cmos.layout b/src/mainboard/google/kahlee/cmos.layout
index c1338d3cdf..b00693dcc2 100644
--- a/src/mainboard/google/kahlee/cmos.layout
+++ b/src/mainboard/google/kahlee/cmos.layout
@@ -58,6 +58,8 @@ entries
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
+#Used by ChromeOS:
+448 128 r 0 vbnv
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers