diff options
| author | Marc Jones <marcj303@gmail.com> | 2017-05-22 21:35:16 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-07-27 21:31:32 +0000 |
| commit | 2d79f16dc81037620ead4e3b49eb470726aec3f2 (patch) | |
| tree | b19cf32c5c2ac9d7104231953cb76ba71f8d981d /src/mainboard/google/kahlee/devicetree.cb | |
| parent | b14e04bd7c492a551532dc3678a1cc922b3cedf8 (diff) | |
| download | coreboot-2d79f16dc81037620ead4e3b49eb470726aec3f2.tar.xz | |
google/kahlee: Start Kahlee mainboard
Copied from amd/gardenia. Update the appropriate board name strings.
Uses the soc/ structure.
Change-Id: Ia68b16969518f4d63d5d2dea7658a472b2daca05
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/kahlee/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/kahlee/devicetree.cb | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/src/mainboard/google/kahlee/devicetree.cb b/src/mainboard/google/kahlee/devicetree.cb new file mode 100644 index 0000000000..bb672b29e6 --- /dev/null +++ b/src/mainboard/google/kahlee/devicetree.cb @@ -0,0 +1,56 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip soc/amd/stoneyridge + + register "spdAddrLookup" = " + { + { {0xA2, 0x00} }, // socket 0 - Channel 0, slots 0 & 1 + }" + + device cpu_cluster 0 on + device lapic 10 on end + end + device domain 0 on + subsystemid 0x1022 0x1410 inherit + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # x4 PCIe slot + device pci 2.2 on end # M.2 slot + device pci 2.3 on end # M.2 slot + device pci 2.4 on end # x1 PCIe slot + device pci 2.5 on end # Cardreader + # devices on the NB/SB Link, but on the same pci bus + device pci 9.0 on end # PCIe Host Bridge + device pci 9.2 on end # HDA + device pci 10.0 on end # xHCI + device pci 11.0 on end # SATA + device pci 12.0 on end # EHCI + device pci 14.0 on # SM + chip drivers/generic/generic # dimm 0-0-0 + device i2c 51 on end + end + end # SM + device pci 14.3 on end # LPC 0x790e + device pci 14.7 on end # SD + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + end #domain +end #chip soc/amd/stoneyridge |