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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-05-02 12:03:45 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-16 10:03:09 +0000 |
| commit | 69486cac74a0e9578c90366feae8abebce5ff834 (patch) | |
| tree | ff4c063d1704e4ddc674fd7c96c2554be97fb6d0 /src/mainboard/google/kahlee/mainboard.c | |
| parent | e1909eea5c4dcf2f67c63d13c2bb74e10d2ba8a2 (diff) | |
| download | coreboot-69486cac74a0e9578c90366feae8abebce5ff834.tar.xz | |
soc/amd/common: Create AcpiMmio functionality from stoneyridge
Move the stoneyridge AcpiMmio code into soc/amd/common.
The SB800 southbridge introduced the MMIO hardware blocks at 0xfed80000
commonly known as AcpiMmio. Implementations beginning with Mullins
enable decode in PMx04. Older designs use PMx24 and allow for
configuring the base address. Future work may support the older version.
Comparing the documentation for AMD's RRGs and BKDGs, it is evident that
the block locations have not been reassigned across products. In some
cases, address locations are deprecated and new ones consumed, e.g. the
early GPIO blocks were simpler at offset 0x100 and the newer GPIO banks
are now at 0x1500, 0x1600, and 0x1700.
Note: Do not infer the definitions within the hardware blocks are
consistent across family/model products.
BUG=b:131682806
Change-Id: I083b6339cd29e72289e63c9331a815c46d71600d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32649
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/kahlee/mainboard.c')
| -rw-r--r-- | src/mainboard/google/kahlee/mainboard.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index ad979a567f..cfd5637633 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -27,6 +27,7 @@ #include <soc/nvs.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> +#include <amdblocks/acpimmio.h> #include <variant/ec.h> #include <variant/thermal.h> #include <vendorcode/google/chromeos/chromeos.h> |