diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-05-23 18:57:47 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-07-27 21:32:55 +0000 |
| commit | beb12880a13fabe0a180600424f75402642087be (patch) | |
| tree | baf104a5958a8a97a03e056163ac0f77bf043f0c /src/mainboard/google/kahlee/mainboard.c | |
| parent | ee193362ad6b80d5a3b9823f4840c7c134a239c6 (diff) | |
| download | coreboot-beb12880a13fabe0a180600424f75402642087be.tar.xz | |
google/kahlee: Add ChromeOS and ChromeEC
Add the basics for building as a ChromeOS device. ChromeOS
and ChromeEC are dependent on each other, so bring them in
together. The EC is a Nuvoton and you can find additional
details in the Chromium EC repo.
Add the Google HWID "Kahlee TEST 6421".
The chromeos.fmd for Kahlee takes advantage of the AGESA
located outside cbfs and includes typical RW, VPD, and
MRC areas.
There are some updates required to depthcharge, vboot, GPIOs,
and the ChromeEC before we have a complete-ish system.
Change-Id: Ifb0a6afc01dd80ef9e7bb81039d9152936043999
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/kahlee/mainboard.c')
| -rw-r--r-- | src/mainboard/google/kahlee/mainboard.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index 2701726cdd..781a71a393 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2015-2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,6 +18,7 @@ #include <arch/acpi.h> #include <agesawrapper.h> #include <amd_pci_util.h> +#include <ec.h> /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. @@ -78,7 +79,7 @@ static void pirq_setup(void) /************************************************* - * enable the dedicated function in kahlee board. + * Dedicated mainboard function *************************************************/ static void kahlee_enable(device_t dev) { @@ -87,6 +88,8 @@ static void kahlee_enable(device_t dev) /* Initialize the PIRQ data structures for consumption */ pirq_setup(); + + mainboard_ec_init(); } struct chip_operations mainboard_ops = { |