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| author | Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> | 2018-03-07 15:38:14 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-03-09 17:11:20 +0000 |
| commit | 9858bd2e3d511ce943207b1e82a9f75853fa637d (patch) | |
| tree | be6f1366273021dd99276f14bb336b56f6730b2f /src/mainboard/google/kahlee/mainboard.c | |
| parent | 546923f906308a737d7797cb96f183a121ab4e10 (diff) | |
| download | coreboot-9858bd2e3d511ce943207b1e82a9f75853fa637d.tar.xz | |
soc/amd/stoneyridge: Add ACPI MMIO enable function
In preparation for moving AGESA calls out of bootblock:
* Add definitions for needed registers in southbridge.h
* Add function to enable AMD FCH ACPI MMIO regions 0xfed80000 to
0xfed81ffff. Will be called by a later commit.
BUG=b:65442212
BRANCH=master
TEST=abuild, build Gardenia, build boot Grunt (with other changes
to call code not committed at this time)
Change-Id: If26efa6c6f5b562ba898e7d9da4827833310dc26
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25025
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/kahlee/mainboard.c')
0 files changed, 0 insertions, 0 deletions