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authorMartin Roth <martinroth@chromium.org>2018-12-04 15:16:00 -0700
committerPatrick Georgi <pgeorgi@google.com>2018-12-05 14:09:17 +0000
commit03f05cff2f9441cb20e78158e32160ec2e833350 (patch)
tree5cb33ae522c6a2cdcb71b87913f5d61a9761516d /src/mainboard/google/kahlee/variants/baseboard/gpio.c
parent822ffe1ef0223664a27ca560c17d3cb2a47edf36 (diff)
downloadcoreboot-03f05cff2f9441cb20e78158e32160ec2e833350.tar.xz
mainboard/google/kahlee: Add romstage GPIO initialization
Move the backlight initialization from bootblock to romstage BUG=b:120436919 TEST=Careena backlight is enabled Change-Id: Ia4993b993d37afaf9e23d6f3316ba91053732f1d Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/c/30039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/mainboard/google/kahlee/variants/baseboard/gpio.c')
-rw-r--r--src/mainboard/google/kahlee/variants/baseboard/gpio.c15
1 files changed, 12 insertions, 3 deletions
diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
index 7922ea50b9..e9ae28c25b 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c
+++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
@@ -77,9 +77,6 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = {
/* GPIO_132 - CONFIG_STRAP4 */
PAD_GPI(GPIO_132, PULL_NONE),
- /* GPIO_133 - APU_EDP_BKLTEN_L (backlight - Active LOW) */
- PAD_GPO(GPIO_133, HIGH),
-
/* GPIO_136 - UART_PCH_RX_DEBUG_TX */
PAD_NF(GPIO_136, UART0_RXD, PULL_NONE),
@@ -93,6 +90,11 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = {
PAD_GPI(GPIO_142, PULL_NONE),
};
+static const struct soc_amd_gpio gpio_set_stage_rom[] = {
+ /* GPIO_133 - APU_EDP_BKLTEN_L (backlight - Active LOW) */
+ PAD_GPO(GPIO_133, HIGH),
+};
+
static const struct soc_amd_gpio gpio_set_stage_ram[] = {
/* GPIO_0 - EC_PCH_PWR_BTN_ODL */
PAD_NF(GPIO_0, PWR_BTN_L, PULL_UP),
@@ -259,6 +261,13 @@ struct soc_amd_gpio *variant_early_gpio_table(size_t *size)
}
const __weak
+struct soc_amd_gpio *variant_romstage_gpio_table(size_t *size)
+{
+ *size = ARRAY_SIZE(gpio_set_stage_rom);
+ return gpio_set_stage_rom;
+}
+
+const __weak
struct soc_amd_gpio *variant_gpio_table(size_t *size)
{
*size = ARRAY_SIZE(gpio_set_stage_ram);