diff options
author | Martin Roth <martinroth@google.com> | 2017-11-07 13:43:02 -0700 |
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committer | Martin Roth <martinroth@google.com> | 2017-11-13 20:19:38 +0000 |
commit | ac35e622c2974304b538292088f5110c181085f5 (patch) | |
tree | 1929e814cf1da42fd9a167235977d0c2371017a2 /src/mainboard/google/kahlee/variants/baseboard/memory.c | |
parent | e1f4d790e43e62f00edfe70602de0cf4da4b9e92 (diff) | |
download | coreboot-ac35e622c2974304b538292088f5110c181085f5.tar.xz |
mainboard/google/kahlee: Add baseboard framework
BUG=b:68293392
TEST=Build only
Change-Id: Ie4d039b4da10a992fc9dd2b0221fd4a1644aae6a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/kahlee/variants/baseboard/memory.c')
-rw-r--r-- | src/mainboard/google/kahlee/variants/baseboard/memory.c | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/src/mainboard/google/kahlee/variants/baseboard/memory.c b/src/mainboard/google/kahlee/variants/baseboard/memory.c new file mode 100644 index 0000000000..511241f603 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/baseboard/memory.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <gpio.h> /* src/include/gpio.h */ +#include <baseboard/variants.h> +#include <variant/gpio.h> + +size_t __attribute__((weak)) variant_board_id(void) +{ + gpio_t pads[] = { + [3] = MEM_CONFIG3, + [2] = MEM_CONFIG2, + [1] = MEM_CONFIG1, + [0] = MEM_CONFIG0, + }; + + return gpio_pullup_base2_value(pads, ARRAY_SIZE(pads)); +} |