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| author | Kevin Chiu <Kevin.Chiu@quantatw.com> | 2019-11-28 16:29:01 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-29 09:01:08 +0000 |
| commit | fba9f33187842e08dd3bb2b21845d7097b116094 (patch) | |
| tree | 39b520b9692e6fd3d9253c9f5e86e31454dc5d66 /src/mainboard/google/kahlee/variants | |
| parent | a3ce27d3dd65fd937ed9a8c5b9230bcace5b356f (diff) | |
| download | coreboot-fba9f33187842e08dd3bb2b21845d7097b116094.tar.xz | |
mainboard/google/kahlee: add G2 TS support for careena
Add G2 GTCH7503 HID TS support
spec from G2: G7500 / Ver.1.2 (3, April, 2018)
BUG=b:141577276
BRANCH=master
TEST=emerge-grunt coreboot
Change-Id: I91e4f2b934b64b14bca20108037b721288d40942
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37318
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/kahlee/variants')
| -rw-r--r-- | src/mainboard/google/kahlee/variants/careena/devicetree.cb | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/mainboard/google/kahlee/variants/careena/devicetree.cb b/src/mainboard/google/kahlee/variants/careena/devicetree.cb index 635b23735c..3387b6f40b 100644 --- a/src/mainboard/google/kahlee/variants/careena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/careena/devicetree.cb @@ -167,5 +167,19 @@ chip soc/amd/stoneyridge register "has_power_resource" = "1" device i2c 10 on end end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.probed" = "1" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end end end #chip soc/amd/stoneyridge |