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authorMarshall Dawson <marshalldawson3rd@gmail.com>2019-05-29 09:24:18 -0600
committerMartin Roth <martinroth@google.com>2019-06-06 18:50:28 +0000
commit6ab5ed3b66fc215d0d03b19ab02fdcf8613c7d09 (patch)
tree0a1512a069659f4f16412cb21f5357daa047aa38 /src/mainboard/google/kahlee
parenteceaa97b27b04a61dd5fb2e68e0f5ac1367a3c0f (diff)
downloadcoreboot-6ab5ed3b66fc215d0d03b19ab02fdcf8613c7d09.tar.xz
soc/amd/stoneyridge: Move LPC support to common
AMD devices traditionally have the LPC-ISA bus at 14.3 and the definition has been very consistent. Relocate the feature from stoneyridge into common/block. BUG=b:131682806 Change-Id: I8d7175b8642bb17533bb2287b3e3ee3d52e85a75 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32653 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/kahlee')
-rw-r--r--src/mainboard/google/kahlee/bootblock/bootblock.c3
-rw-r--r--src/mainboard/google/kahlee/ec.c3
2 files changed, 4 insertions, 2 deletions
diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c
index 3be308e2d3..e403684a41 100644
--- a/src/mainboard/google/kahlee/bootblock/bootblock.c
+++ b/src/mainboard/google/kahlee/bootblock/bootblock.c
@@ -17,6 +17,7 @@
#include <bootblock_common.h>
#include <soc/gpio.h>
#include <soc/southbridge.h>
+#include <amdblocks/lpc.h>
#include <variant/ec.h>
#include <variant/gpio.h>
@@ -61,5 +62,5 @@ void bootblock_mainboard_init(void)
}
/* Setup TPM decode before verstage */
- sb_tpm_decode_spi();
+ lpc_tpm_decode_spi();
}
diff --git a/src/mainboard/google/kahlee/ec.c b/src/mainboard/google/kahlee/ec.c
index 7164591e11..1080902702 100644
--- a/src/mainboard/google/kahlee/ec.c
+++ b/src/mainboard/google/kahlee/ec.c
@@ -16,6 +16,7 @@
#include <arch/acpi.h>
#include <console/console.h>
#include <ec/google/chromeec/ec.h>
+#include <amdblocks/lpc.h>
#include <soc/southbridge.h>
#include <variant/ec.h>
@@ -49,7 +50,7 @@ static void early_ec_init(void)
printk(BIOS_DEBUG,
"LPC Setup google_chromeec_ioport_range: %04x, %08zx\n",
ec_ioport_base, ec_ioport_size);
- status = sb_set_wideio_range(ec_ioport_base, ec_ioport_size);
+ status = lpc_set_wideio_range(ec_ioport_base, ec_ioport_size);
if (status == WIDEIO_RANGE_ERROR)
printk(BIOS_WARNING, "ERROR: Failed to assign a range\n");
else