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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-25 21:23:37 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-28 21:50:12 +0000 |
| commit | 5b672d595411a50012d3d232db6d886818d44893 (patch) | |
| tree | 06ead78b90df1ec04fe71c29f52068290821f115 /src/mainboard/google/kahlee | |
| parent | b0ae42b5bb7fe7c9f6e8301bff8fbabe95294c62 (diff) | |
| download | coreboot-5b672d595411a50012d3d232db6d886818d44893.tar.xz | |
soc/amd/common: Access ACPIMMIO via proper symbols
Using proper symbols for base addresses, it is possible to
only define the symbols for base addresses implemented for
the specific platform and executing stage.
Change-Id: Ib8599ee93bfb1c2d6d9b4accfca1ebbefe758e09
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/kahlee')
| -rw-r--r-- | src/mainboard/google/kahlee/mainboard.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index 239887e167..5e1bdf4c2d 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -134,13 +134,13 @@ static void mainboard_init(void *chip_info) pm_write8(PM_PCIB_CFG, pm_read8(PM_PCIB_CFG) | PM_GENINT_DISABLE); /* Set low-power mode for BayHub eMMC bridge's PCIe clock. */ - clrsetbits32((uint32_t *)(ACPIMMIO_MISC_BASE + GPP_CLK_CNTRL), + clrsetbits32(acpimmio_misc + GPP_CLK_CNTRL, GPP_CLK2_REQ_MAP_MASK, GPP_CLK2_REQ_MAP_CLK_REQ2 << GPP_CLK2_REQ_MAP_SHIFT); /* Same for the WiFi */ - clrsetbits32((uint32_t *)(ACPIMMIO_MISC_BASE + GPP_CLK_CNTRL), + clrsetbits32(acpimmio_misc + GPP_CLK_CNTRL, GPP_CLK0_REQ_MAP_MASK, GPP_CLK0_REQ_MAP_CLK_REQ0 << GPP_CLK0_REQ_MAP_SHIFT); |