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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-09-25 12:04:18 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-11-10 22:01:28 +0000 |
| commit | f79b636088d36f1a6ac58f02e58ad8561899bb31 (patch) | |
| tree | acb9f9bc4c8e096f237bb183781f63d6d93f7116 /src/mainboard/google/kahlee | |
| parent | 36dbf1d74a8797b49984c98df748c1d526831e53 (diff) | |
| download | coreboot-f79b636088d36f1a6ac58f02e58ad8561899bb31.tar.xz | |
google/kahlee: Use devicetree register values for UMA
Set the UMA memory size to 128 MiB. This value was empirically tested
by AMD as the lowest value one could use.
BUG=b:64927639
TEST=default, and 64, 128, 256, 384MB non-legacy configurations.
Change-Id: I2bc808d8b402c3eb16a1a5962f3fa9d6b224cf52
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21335
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/kahlee')
| -rw-r--r-- | src/mainboard/google/kahlee/variants/kahlee/devicetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/kahlee/variants/kahlee/devicetree.cb b/src/mainboard/google/kahlee/variants/kahlee/devicetree.cb index c4535225e2..28f22a4c79 100644 --- a/src/mainboard/google/kahlee/variants/kahlee/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/kahlee/devicetree.cb @@ -19,6 +19,8 @@ chip soc/amd/stoneyridge { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0 }" register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" + register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" + register "uma_size" = "128 * MiB" device cpu_cluster 0 on device lapic 10 on end |