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authorGabe Black <gabeblack@google.com>2013-07-30 21:35:31 -0700
committerPatrick Georgi <patrick@georgi-clan.de>2013-12-21 19:56:56 +0100
commit9245440eaf6d77175a76b68162917997a3152d24 (patch)
treeef7a44c44690a5006dcf64f9736898a1be223055 /src/mainboard/google/kirby/devicetree.cb
parent74dbfc252ff07a9c9b7fcf4511e561991d5bd46d (diff)
downloadcoreboot-9245440eaf6d77175a76b68162917997a3152d24.tar.xz
Add a kirby board which is mostly a copy of pit
Change-Id: Ic78c65486816015f7574a13affc6e54acbbea73e Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63875 Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4411 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/google/kirby/devicetree.cb')
-rw-r--r--src/mainboard/google/kirby/devicetree.cb35
1 files changed, 35 insertions, 0 deletions
diff --git a/src/mainboard/google/kirby/devicetree.cb b/src/mainboard/google/kirby/devicetree.cb
new file mode 100644
index 0000000000..2c9e668fe5
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+++ b/src/mainboard/google/kirby/devicetree.cb
@@ -0,0 +1,35 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2013 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+chip cpu/samsung/exynos5420
+ device cpu_cluster 0 on end
+ register "xres" = "1366"
+ register "yres" = "768"
+ register "bpp" = "16"
+ # complex magic timing!
+ register "clkval_f" = "2"
+ register "upper_margin" = "14"
+ register "lower_margin" = "3"
+ register "vsync" = "5"
+ register "left_margin" = "80"
+ register "right_margin" = "48"
+ register "hsync" = "32"
+ register "usb_vbus_gpio" = "GPIO_X11"
+ register "usb_hsic_gpio" = "GPIO_E10"
+end