diff options
| author | Junzhi Zhao <junzhi.zhao@mediatek.com> | 2018-06-13 16:20:00 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-03 22:23:10 +0000 |
| commit | 66ee65f0368e095fb305e0e84bf69e4c9aede358 (patch) | |
| tree | ad22e1b04a15d8c493a870b0cfd43ca4c26f4743 /src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c | |
| parent | 4d15d2fc122a3548099504fc1f49d70087ac45ad (diff) | |
| download | coreboot-66ee65f0368e095fb305e0e84bf69e4c9aede358.tar.xz | |
google/kukui: Initialize DRAM from romstage
Add DRAM support for google kukui.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: I1ed01404343745c883b22a648966327bdcabc5c2
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/28438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c')
| -rw-r--r-- | src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c new file mode 100644 index 0000000000..da6c7d255e --- /dev/null +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/emi.h> + +struct sdram_params params = { + .impedance = { + [ODT_OFF] = {0x7, 0x6, 0x0, 0xF}, + [ODT_ON] = {0x9, 0x9, 0x0, 0xF} + }, + .wr_level = { + [CHANNEL_A] = { {0x22, 0x1b}, {0x22, 0x19} }, + [CHANNEL_B] = { {0x24, 0x20}, {0x25, 0x20} } + }, + .cbt_cs = { + [CHANNEL_A] = {0x0, 0x0}, + [CHANNEL_B] = {0x0, 0x0} + }, + .cbt_mr12 = { + [CHANNEL_A] = {0x52, 0x52}, + [CHANNEL_B] = {0x52, 0x52} + }, + .emi_cona_val = 0xF053F154, + .emi_conh_val = 0x44440003, + .emi_conf_val = 0x00421000, + .chn_emi_cona_val = {0x0444F051, 0x0444F051}, + .cbt_mode_extern = CBT_NORMAL_MODE, + .delay_cell_unit = 868, +}; |