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authorHuayang Duan <huayang.duan@mediatek.com>2019-08-27 13:36:14 +0800
committerPatrick Georgi <pgeorgi@google.com>2019-10-09 22:22:41 +0000
commit078332e4d82a9a2edfa4e3fbcdc8b0b78356f989 (patch)
treef5f576fa261890f34eae1648d9224ef6fe1f3be8 /src/mainboard/google/kukui
parent846be446d3099544c2d1029ca2b7884c1641441d (diff)
downloadcoreboot-078332e4d82a9a2edfa4e3fbcdc8b0b78356f989.tar.xz
soc/mediatek/mt8183: Run DRAM full calibration
Load the calibration params from flash first and check the correctness of the params. If the params have correct format, perform DRAM fast calibration with these params to reduce bootup time. Otherwise, load the DRAM blob and perform DRAM full calibration. Bootup time of DRAM partial calibration: - 1,349,385 usecs with low frequency - 924,698 usecs with middle frequency - 1,270,089 usecs with high frequency 3,544,172 usecs in total. Bootup time of DRAM fast calibration: - 216,663 usecs with low frequency - 328,220 usecs with middle frequency - 322,612 usecs with high frequency 867,495 usecs in total. BUG=b:139099592 BRANCH=none TEST=emerge-kukui coreboot Change-Id: I8de29b14b1fb24b3b4f351c855c5c4d8f350cc34 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/mainboard/google/kukui')
-rw-r--r--src/mainboard/google/kukui/romstage.c41
1 files changed, 40 insertions, 1 deletions
diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c
index a86690b6fb..2b7dd6a20c 100644
--- a/src/mainboard/google/kukui/romstage.c
+++ b/src/mainboard/google/kukui/romstage.c
@@ -14,6 +14,9 @@
*/
#include <arch/stages.h>
+#include <console/console.h>
+#include <fmap.h>
+#include <soc/dramc_param.h>
#include <soc/emi.h>
#include <soc/mmu_operations.h>
#include <soc/mt6358.h>
@@ -22,6 +25,42 @@
#include "early_init.h"
+/* This must be defined in chromeos.fmd in same name and size. */
+#define CALIBRATION_REGION "RW_DDR_TRAINING"
+#define CALIBRATION_REGION_SIZE 0x2000
+
+_Static_assert(sizeof(struct dramc_param) <= CALIBRATION_REGION_SIZE,
+ "sizeof(struct dramc_param) exceeds " CALIBRATION_REGION);
+
+static bool read_calibration_data_from_flash(struct dramc_param *dparam)
+{
+ const size_t length = sizeof(*dparam);
+ size_t ret = fmap_read_area(CALIBRATION_REGION, dparam, length);
+ printk(BIOS_DEBUG, "%s: ret=%#lx, length=%#lx\n",
+ __func__, ret, length);
+
+ return ret == length;
+}
+
+static bool write_calibration_data_to_flash(const struct dramc_param *dparam)
+{
+ const size_t length = sizeof(*dparam);
+ size_t ret = fmap_overwrite_area(CALIBRATION_REGION, dparam, length);
+ printk(BIOS_DEBUG, "%s: ret=%#lx, length=%#lx\n",
+ __func__, ret, length);
+
+ return ret == length;
+}
+
+/* dramc_param is ~2K and too large to fit in stack. */
+static struct dramc_param dramc_parameter;
+
+static struct dramc_param_ops dparam_ops = {
+ .param = &dramc_parameter,
+ .read_from_flash = &read_calibration_data_from_flash,
+ .write_to_flash = &write_calibration_data_to_flash,
+};
+
void platform_romstage_main(void)
{
/* This will be done in verstage if CONFIG_VBOOT is enabled. */
@@ -34,6 +73,6 @@ void platform_romstage_main(void)
mt_pll_raise_ca53_freq(1989 * MHz);
pmic_init_scp_voltage();
rtc_boot();
- mt_mem_init(get_sdram_config());
+ mt_mem_init(&dparam_ops);
mtk_mmu_after_dram();
}