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| author | Matt DeVillier <matt.devillier@gmail.com> | 2018-07-07 19:03:06 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-07-21 00:49:52 +0000 |
| commit | 357ea55f454a77dd5c2a9b14e5d7d5946b433146 (patch) | |
| tree | d4440490f46869dddaeb620ecf975eef89869e54 /src/mainboard/google/lars/dsdt.asl | |
| parent | 39f3c7e1840823c294d7cedf11aed62bdd765141 (diff) | |
| download | coreboot-357ea55f454a77dd5c2a9b14e5d7d5946b433146.tar.xz | |
google/lars: Convert to a variant of glados
Convert lars to a variant of glados Skylake reference board:
- add lars-specific DPTF, EC config, GPIO config, Kconfig,
NHLT config, PEI data, VBT, SPD data, and devicetree
- add conditional generation of NHLT ACPI data for Maxim codec,
including override of OEM ID and OEM table ID
- remove existing lars board/directory
Test: build/boot google/lars, verify functionality unchanged
from pre-variant configuration
Change-Id: Iab37f1b92b0f3a5d99796f916a6fdcc14ce4eef4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27413
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/lars/dsdt.asl')
| -rw-r--r-- | src/mainboard/google/lars/dsdt.asl | 55 |
1 files changed, 0 insertions, 55 deletions
diff --git a/src/mainboard/google/lars/dsdt.asl b/src/mainboard/google/lars/dsdt.asl deleted file mode 100644 index b5a37c68cc..0000000000 --- a/src/mainboard/google/lars/dsdt.asl +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x05, // DSDT revision: ACPI v5.0 - "COREv4", // OEM id - "COREBOOT", // OEM table id - 0x20110725 // OEM revision -) -{ - // Some generic macros - #include <soc/intel/skylake/acpi/platform.asl> - - // global NVS and variables - #include <soc/intel/skylake/acpi/globalnvs.asl> - - // CPU - #include <soc/intel/skylake/acpi/cpu.asl> - - Scope (\_SB) { - Device (PCI0) - { - #include <soc/intel/skylake/acpi/systemagent.asl> - #include <soc/intel/skylake/acpi/pch.asl> - } - - // Dynamic Platform Thermal Framework - #include "acpi/dptf.asl" - } - - // Chrome OS specific - #include <vendorcode/google/chromeos/acpi/chromeos.asl> - - // Chipset specific sleep states - #include <soc/intel/skylake/acpi/sleepstates.asl> - - // Mainboard specific - #include "acpi/mainboard.asl" -} |