diff options
| author | david <david_wu@quantatw.com> | 2015-10-23 20:22:22 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-10-28 22:27:36 +0100 |
| commit | f372fb5529173817664db405055fda8895518620 (patch) | |
| tree | c3de8dc338f3b495fc7309ee2f7ba2deb9b40e82 /src/mainboard/google/lars/gpio.h | |
| parent | ad038c1a14d595c88fb0b4bb6f420e4490b0a67a (diff) | |
| download | coreboot-f372fb5529173817664db405055fda8895518620.tar.xz | |
google/lars: Add new mainboard
This is based on kunimitsu with minor changes:
- update GPIOs based on schematic
- update SPD data for memory config
- disable ALS
BUG=None
TEST=emerge-lars coreboot
Change-Id: Id1c9edfe3cc665e90683344f1662de2e65caf766
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3201aa573a77fcad3b6b1335d23eb4c2a09c1708
Original-Change-Id: Ifae446e4668569b6100b29bc1f52b0fea1df2952
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/308283
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/12201
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/lars/gpio.h')
| -rwxr-xr-x | src/mainboard/google/lars/gpio.h | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/src/mainboard/google/lars/gpio.h b/src/mainboard/google/lars/gpio.h index 3c4c127fa0..77ac8cda7f 100755 --- a/src/mainboard/google/lars/gpio.h +++ b/src/mainboard/google/lars/gpio.h @@ -70,8 +70,8 @@ static const struct pad_config gpio_table[] = { /* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* PM_SUS_STAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), -/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), -/* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), +/* SD_1P8_SEL */ /* GPP_A16 */ +/* SD_PWR_EN */ /* GPP_A17 */ /* ACCEL INTERRUPT */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* ISH_GP1 */ /* GPP_A19 */ /* GYRO_DRDY */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), @@ -178,12 +178,12 @@ static const struct pad_config gpio_table[] = { /* I2S2_SFRM */ PAD_CFG_GPI(GPP_F1, NONE, DEEP), /* I2S2_TXD */ PAD_CFG_GPI(GPP_F2, NONE, DEEP), /* I2S2_RXD */ PAD_CFG_GPI(GPP_F3, NONE, DEEP), -/* I2C2_SDA */ /* GPP_F4 */ -/* I2C2_SCL */ /* GPP_F5 */ +/* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), +/* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* I2C3_SDA */ /* GPP_F6 */ /* I2C3_SCL */ /* GPP_F7 */ /* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), -/* I2C4_SDA */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), +/* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP), /* I2C5_SCL */ /* GPP_F11 */ /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), @@ -198,14 +198,14 @@ static const struct pad_config gpio_table[] = { /* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* GPP_F23 */ -/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), -/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), -/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), -/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), -/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), -/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), -/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), -/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), +/* SD_CMD */ /* GPP_G0 */ +/* SD_DATA0 */ /* GPP_G1 */ +/* SD_DATA1 */ /* GPP_G2 */ +/* SD_DATA2 */ /* GPP_G3 */ +/* SD_DATA3 */ /* GPP_G4 */ +/* SD_CD# */ /* GPP_G5 */ +/* SD_CLK */ /* GPP_G6 */ +/* SD_WP */ /* GPP_G7 */ /* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), |