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authorSumeet Pawnikar <sumeet.r.pawnikar@intel.com>2016-10-18 11:07:39 +0530
committerMartin Roth <martinroth@google.com>2016-11-07 20:43:00 +0100
commit94f50dee63965a48ee70f80204076845cdc58d1d (patch)
tree44632c82e0a9d7f8981a8b6548a9b9d7a1965134 /src/mainboard/google/lars
parentbc41ddd44eec93700d8aeffad1c9fc4b19cea9d8 (diff)
downloadcoreboot-94f50dee63965a48ee70f80204076845cdc58d1d.tar.xz
google/lars: Update DPTF settings
After tuning the temperature values for optimal performance, this patch updates few DPTF settings for lars boards. BUG=chrome-os-partner:51025 BRANCH=firmware-glados-7820.B TEST=Built and booted on lars DVT boards. Verified these updated DPTF settings with different workloads. Change-Id: I4c040526c31c3263ed3a9b4cccff3b7a021cfcdb Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://chromium-review.googlesource.com/338877 Reviewed-on: https://review.coreboot.org/17068 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/lars')
-rw-r--r--src/mainboard/google/lars/acpi/dptf.asl20
1 files changed, 10 insertions, 10 deletions
diff --git a/src/mainboard/google/lars/acpi/dptf.asl b/src/mainboard/google/lars/acpi/dptf.asl
index b8f0a7a475..82a23f8936 100644
--- a/src/mainboard/google/lars/acpi/dptf.asl
+++ b/src/mainboard/google/lars/acpi/dptf.asl
@@ -14,15 +14,15 @@
* GNU General Public License for more details.
*/
-#define DPTF_CPU_PASSIVE 95
+#define DPTF_CPU_PASSIVE 94
#define DPTF_CPU_CRITICAL 99
#define DPTF_CPU_ACTIVE_AC0 90
#define DPTF_CPU_ACTIVE_AC1 77
#define DPTF_TSR0_SENSOR_ID 0
#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal"
-#define DPTF_TSR0_PASSIVE 65
-#define DPTF_TSR0_CRITICAL 70
+#define DPTF_TSR0_PASSIVE 66
+#define DPTF_TSR0_CRITICAL 71
#define DPTF_TSR0_ACTIVE_AC0 120
#define DPTF_TSR0_ACTIVE_AC1 110
#define DPTF_TSR0_ACTIVE_AC2 47
@@ -33,13 +33,13 @@
#define DPTF_TSR1_SENSOR_ID 1
#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top"
-#define DPTF_TSR1_PASSIVE 63
-#define DPTF_TSR1_CRITICAL 68
+#define DPTF_TSR1_PASSIVE 75
+#define DPTF_TSR1_CRITICAL 80
#define DPTF_TSR2_SENSOR_ID 2
#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom"
-#define DPTF_TSR2_PASSIVE 64
-#define DPTF_TSR2_CRITICAL 69
+#define DPTF_TSR2_PASSIVE 65
+#define DPTF_TSR2_CRITICAL 70
#define DPTF_ENABLE_CHARGER
#define DPTF_ENABLE_FAN_CONTROL
@@ -83,12 +83,12 @@ Name (DART, Package () {
* Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6,
* AC7, AC8, AC9
*/
- \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 100, 81, 0, 0, 0, 0, 0,
+ \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 100, 72, 0, 0, 0, 0, 0,
0, 0, 0
},
Package () {
- \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 100, 81, 68, 56, 48, 40,
- 35, 0, 0, 0
+ \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 100, 72, 68, 49, 39, 38,
+ 37, 0, 0, 0
}
})
#endif