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authorSubrata Banik <subrata.banik@intel.com>2018-05-09 14:55:09 +0530
committerSubrata Banik <subrata.banik@intel.com>2018-06-06 06:23:45 +0000
commitc4986eb7f4eee0f305c6a6f05b45effae152062c (patch)
tree46185566d98e49bbfa60acfdedc60e1e423823d3 /src/mainboard/google/lars
parentf513cebd8b966c15e3c8abcd2d0f540607ea5964 (diff)
downloadcoreboot-c4986eb7f4eee0f305c6a6f05b45effae152062c.tar.xz
soc/intel/common/block: Add common chip config block
Adding common chip config structure which will be used to return data to common code. When common code requires soc data, code used to fetch entire soc config structure. With this change, common code will only get the data/structure which is required by common code and not entire config. For now, adding i2c, gspi and lockdown configuration which will be used by common code. BUG=none BRANCH=b:78109109 TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check values are returned properly using common structure. Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/26189 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/lars')
-rw-r--r--src/mainboard/google/lars/devicetree.cb4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb
index c860569c9b..6bb460ae3c 100644
--- a/src/mainboard/google/lars/devicetree.cb
+++ b/src/mainboard/google/lars/devicetree.cb
@@ -184,7 +184,9 @@ chip soc/intel/skylake
register "SendVrMbxCmd" = "2"
# Lock Down
- register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
+ register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+ }"
device cpu_cluster 0 on
device lapic 0 on end