chromeos mainboards: remove chromeos.asl

Use the ACPI generator for creating the Chrome OS gpio
package. Each mainboard has its own list of Chrome OS
gpios that are fed into a helper to generate the ACPI
external OIPG package.  Additionally, the common
chromeos.asl is now conditionally included based on
CONFIG_CHROMEOS.

Change-Id: I1d3d951964374a9d43521879d4c265fa513920d2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15909
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

4 files changed, 12 insertions, 25 deletions

diff --git a/src/mainboard/google/lars/acpi/chromeos.asl b/src/mainboard/google/lars/acpi/chromeos.asl
deleted file mode 100644
index 4fc5f22984..0000000000
--- a/src/mainboard/google/lars/acpi/chromeos.asl
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include "../gpio.h"
-
-Name (OIPG, Package () {
-	/* No physical recovery GPIO. */
-	Package () { 0x0001, 0, 0xFFFFFFFF, "INT344B:00" },
-	/* Firmware write protect GPIO. */
-	Package () { 0x0003, 1, GPIO_PCH_WP, "INT344B:00" },
-})
diff --git a/src/mainboard/google/lars/chromeos.c b/src/mainboard/google/lars/chromeos.c
index 1e0bd3c093..daa85c69e0 100644
--- a/src/mainboard/google/lars/chromeos.c
+++ b/src/mainboard/google/lars/chromeos.c
@@ -82,3 +82,13 @@ int get_write_protect_state(void)
 	/* Read PCH_WP GPIO. */
 	return gpio_get(GPIO_PCH_WP);
 }
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/google/lars/dsdt.asl b/src/mainboard/google/lars/dsdt.asl
index c9e13e7e45..b5a37c68cc 100644
--- a/src/mainboard/google/lars/dsdt.asl
+++ b/src/mainboard/google/lars/dsdt.asl
@@ -45,7 +45,6 @@ DefinitionBlock(
 	}
 
 	// Chrome OS specific
-	#include "acpi/chromeos.asl"
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
 	// Chipset specific sleep states
diff --git a/src/mainboard/google/lars/mainboard.c b/src/mainboard/google/lars/mainboard.c
index 6725f134d3..e0444059bf 100644
--- a/src/mainboard/google/lars/mainboard.c
+++ b/src/mainboard/google/lars/mainboard.c
@@ -20,6 +20,7 @@
 #include <device/device.h>
 #include <stdlib.h>
 #include <soc/nhlt.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 #include "ec.h"
 
 static void mainboard_init(device_t dev)
@@ -69,6 +70,7 @@ static void mainboard_enable(device_t dev)
 {
 	dev->ops->init = mainboard_init;
 	dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 }
 
 struct chip_operations mainboard_ops = {