diff options
| author | david <david_wu@quantatw.com> | 2015-12-09 15:29:06 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-01-18 12:03:52 +0100 |
| commit | d4fd0a0fc13453b91342c02877363842acb38fc6 (patch) | |
| tree | b289ef5e628c7c42bad1bf4d83e715cd21b30718 /src/mainboard/google/lars | |
| parent | 30f53cd3973886fb69a59479231656846e11e5ca (diff) | |
| download | coreboot-d4fd0a0fc13453b91342c02877363842acb38fc6.tar.xz | |
google/lars: Correct the output for crossystem wpsw_boot
The write protect GPIO is not being configured early enough.
This is leading to coreboot reading incorrect value, and
writing the incorrect value in vboot shared file.
This is leading to "crossystem wpsw_boot" always returning 0
even with the write protect screw in place during boot.
BRANCH=none
BUG=chrome-os-partner:48292
TEST=Build and boot on lars
Change-Id: I28fbbd690ca6efb539422e9ba02f10e07cd35346
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d229ba9d8934dcb5f22b27ce0ad27601ec87d6ff
Original-Change-Id: I64f2497a6bb3a50b0f58c67e2ab6751c4836fd89
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/317130
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12966
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/lars')
| -rwxr-xr-x | src/mainboard/google/lars/gpio.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/lars/gpio.h b/src/mainboard/google/lars/gpio.h index acb04ec01d..5aee2373c8 100755 --- a/src/mainboard/google/lars/gpio.h +++ b/src/mainboard/google/lars/gpio.h @@ -226,6 +226,7 @@ static const struct pad_config gpio_table[] = { static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ +/* SPI_WP_STATUS */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), }; #endif |