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authorFurquan Shaikh <furquan@chromium.org>2016-10-04 10:53:32 -0700
committerMartin Roth <martinroth@google.com>2016-10-07 18:05:30 +0200
commit028200f75f6d8d0f947d68f41ca10fbfe05f9283 (patch)
treec56f256737b61702dbab15e0ba53a6c0766c8342 /src/mainboard/google/lars
parent35c01bc4e0bc72d4ba8bafc922b47f9aa47ca02d (diff)
downloadcoreboot-028200f75f6d8d0f947d68f41ca10fbfe05f9283.tar.xz
x86/acpi_device: Add support for GPIO output polarity
Instead of hard-coding the polarity of the GPIO to active high/low, accept it as a parameter in devicetree. This polarity can then be used while calling into acpi_dp_add_gpio to determine the active low status correctly. BUG=chrome-os-partner:55988 BRANCH=None TEST=Verified that correct polarity is set for reset-gpio on reef. Change-Id: I4aba4bb8bd61799962deaaa11307c0c5be112919 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/16877 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/google/lars')
-rw-r--r--src/mainboard/google/lars/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb
index e1e926be00..25bd19d9d6 100644
--- a/src/mainboard/google/lars/devicetree.cb
+++ b/src/mainboard/google/lars/devicetree.cb
@@ -279,7 +279,7 @@ chip soc/intel/skylake
device pci 1f.2 on end # Power Management Controller
device pci 1f.3 on
chip drivers/generic/max98357a
- register "sdmode_gpio" = "ACPI_GPIO_OUTPUT(GPP_B2)"
+ register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)"
device generic 0 on end
end
end # Intel HDA