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| author | Matt DeVillier <matt.devillier@gmail.com> | 2018-02-01 00:39:53 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-02-05 19:50:06 +0000 |
| commit | e5eaa4b5a5dfaf7081d5656823c5bf428e9b8648 (patch) | |
| tree | c0d85d253a7527b0a938146b511fbde8748550af /src/mainboard/google/lars | |
| parent | ea942169f9af8afe10a450c06045c98a8bb40a7f (diff) | |
| download | coreboot-e5eaa4b5a5dfaf7081d5656823c5bf428e9b8648.tar.xz | |
google/lars: update device properties for Nuvoton codec
Adapted from Chromium commit:
848ee3a [Lars: Add device properties for Nuvoton codec]
Update sar-threshold, sar-compare-time, sar-sampling-time
properties to match values in lars' Chromium branch.
Adaptation needed to account for parameters having moved
from mainboard.asl to devicetree in upstream tree.
Original-Change-Id: Id0c28e50406a29e6f33d04ca78fd2a3e3974fa90
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Benson Leung <bleung@chromium.org>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Change-Id: I2748a315d27eb947197109808b4d5fa8a82c8cf3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/lars')
| -rw-r--r-- | src/mainboard/google/lars/devicetree.cb | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb index 99522cbe3e..64f2a61f97 100644 --- a/src/mainboard/google/lars/devicetree.cb +++ b/src/mainboard/google/lars/devicetree.cb @@ -233,14 +233,14 @@ chip soc/intel/skylake register "vref_impedance" = "2" # 125kOhm register "micbias_voltage" = "6" # 2.754 register "sar_threshold_num" = "4" - register "sar_threshold[0]" = "0x0a" - register "sar_threshold[1]" = "0x14" + register "sar_threshold[0]" = "0x08" + register "sar_threshold[1]" = "0x12" register "sar_threshold[2]" = "0x26" register "sar_threshold[3]" = "0x73" register "sar_hysteresis" = "0" register "sar_voltage" = "6" - register "sar_compare_time" = "0" # 500ns - register "sar_sampling_time" = "0" # 2us + register "sar_compare_time" = "1" # 1us + register "sar_sampling_time" = "1" # 4us register "short_key_debounce" = "3" # 30ms register "jack_insert_debounce" = "7" # 512ms register "jack_eject_debounce" = "0" |