summaryrefslogtreecommitdiff
path: root/src/mainboard/google/lars
diff options
context:
space:
mode:
authorAaron Durbin <adurbin@chromium.org>2016-11-09 17:04:15 -0600
committerAaron Durbin <adurbin@chromium.org>2016-11-11 03:11:31 +0100
commited14a4e0df25e55cea2b72a87087aaeb3540c785 (patch)
tree5a60bd779391096d6554d9b94f384f158d7c3c00 /src/mainboard/google/lars
parentce21151a1c050476079c3ce31b8e8013f8cd3282 (diff)
downloadcoreboot-ed14a4e0df25e55cea2b72a87087aaeb3540c785.tar.xz
soc/intel/skylake: move i2c voltage config to own variable
In preparation of merging the lpss i2c config structures on apollolake and skylake move the i2c voltage variable to its own field. It makes refactoring things easier, and then there's no reason for a separate SoC specific i2c config structure. BUG=chrome-os-partner:58889 Change-Id: Ibcc3cba9bac3b5779351b673bc0cc7671d127f24 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17347 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/mainboard/google/lars')
-rw-r--r--src/mainboard/google/lars/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb
index 25bd19d9d6..dab95de41a 100644
--- a/src/mainboard/google/lars/devicetree.cb
+++ b/src/mainboard/google/lars/devicetree.cb
@@ -160,7 +160,7 @@ chip soc/intel/skylake
register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port (card)
register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port (board)
- register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
+ register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{ \