link/graphics: New state machine

This is a new state machine. It is more programmatic, in the
case of auxio, and has much more symbolic naming, and very few
"magic" numbers, except in the case of undocumented settings.

As before, the 'pre-computed' IO ops are encoded in the iodefs
table. A function, run, is passed and index into the table and
runs the ops.

A new operator, I, has been added. When the I operator is hit,
run() returns the index of the next operator in the table.

The i915lightup function runs the table. All the AUX channel ops
have been removed from the table, however, and are now called as
functions, using the previously committed auxio function.

The iodefs table has been grouped into blocks of ops, which end in
an I operator. As the lightup function progresses through startup,
and the run() returns, the lightup function performs aux channel
operations.

This code is symbolic enough, I hope, that it will make haswell
graphics bringup simpler.

i915io.c, and the core of the code in i915lightup.c, were
programatically generated, starting with IO logs from the DRM
startup code in the kernel. It is possible to apply the tools that
do this generation to newer IO logs from the kernel.

Change-Id: I8a8e121dc0d9674f0c6a866343b28e179a1e3d8a
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2836
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 335 insertions, 478 deletions

diff --git a/src/mainboard/google/link/i915io.c b/src/mainboard/google/link/i915io.c
index eaa2e94508..308ace6fcc 100644
--- a/src/mainboard/google/link/i915io.c
+++ b/src/mainboard/google/link/i915io.c
@@ -16,485 +16,342 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
+
 #include <stdint.h>
 #include "i915io.h"
 
 struct iodef iodefs[] = {
-{V,0,},
-//{V, 7, },
-{W, 1, "", PCH_GMBUS0, 0x00000000, },
-{R, 1, "", PP_ON_DELAYS, 0x00000000, },
-{R, 1, "", PP_OFF_DELAYS, 0x00000000, },
-{W, 1, "", PP_ON_DELAYS, 0x019007d0, },
-{W, 1, "", PP_OFF_DELAYS, 0x015e07d0, },
-{M, 1, "[drm:intel_detect_pch], Found PatherPoint PCH"},
-{M, 1, "[drm:i915_load_modeset_init], failed to find VBIOS tables"},
-{R, 50, "", 0x130040, 0x00000001,  10},
-{W, 1, "", 0xa188, 0x00010001, },
-{R, 1, "", 0xa188, 0x00010001, },
-{R, 1, "", 0x130040, 0x00000001, },
-{R, 1, "", 0x13805c, 0x40000000, },
-{R, 1, "", 0xa180, 0x84100020, },
-{W, 1, "", 0xa188, 0x00010000, },
-{R, 1, "", 0x120000, 0x00000000, },
-{M, 1, "[drm:intel_init_display], Using MT version of forcewake"},
-{R, 1, "", 0x145d10, 0x2010040c, },
-{M, 1, "[drm:intel_modeset_init], 3 display pipes available."},
-{R, 1, "", _PIPEACONF, 0x00000000, },
-{W, 1, "", _PIPEACONF, 0x00000000, },
-{R, 1, "", _PIPEBCONF, 0x00000000, },
-{W, 1, "", _PIPEBCONF, 0x00000000, },
-{R, 1, "", 0x72008, 0x00000000, },
-{W, 1, "", 0x72008, 0x00000000, },
-{R, 1, "", _PIPEACONF, 0x00000000, },
-{W, 1, "", _PIPEACONF, 0x00000000, },
-{R, 1, "", _PIPEBCONF, 0x00000000, },
-{W, 1, "", _PIPEBCONF, 0x00000000, },
-{R, 1, "", 0x72008, 0x00000000, },
-{W, 1, "", 0x72008, 0x00000000, },
-{R, 1, "", _PIPEACONF, 0x00000000, },
-{W, 1, "", _PIPEACONF, 0x00000000, },
-{R, 1, "", _PIPEBCONF, 0x00000000, },
-{W, 1, "", _PIPEBCONF, 0x00000000, },
-{R, 1, "", 0x72008, 0x00000000, },
-{W, 1, "", 0x72008, 0x00000000,  300},
-{W, 1, "", CPU_VGACNTRL, 0x80000000, },
-{R, 1, "", CPU_VGACNTRL, 0x80000000, },
-{R, 1, "", 0x64000, 0x0000001c, },
-{R, 1, "", PCH_PP_ON_DELAYS, 0x47d007d0, },
-{R, 1, "", PCH_PP_OFF_DELAYS, 0x01f407d0, },
-{R, 1, "", PCH_PP_DIVISOR, 0x00186906, },
-{M, 1, "[drm:intel_dp_init], cur t1_t3 2000 t8 2000 t9 2000 t10 500"
-    "t11_t12 6000"},
-{M, 1, "[drm:intel_dp_init], vbt t1_t3 0 t8 0 t9 0 t10 0 t11_t12 0"},
-{M, 1, "[drm:intel_dp_init], panel power up delay 200,"
-    "power down delay 50, power cycle delay 600"},
-{M, 1, "[drm:intel_dp_init], backlight on delay 200, off delay 200"},
-{M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on"},
-{R, 1, "", PCH_PP_CONTROL, 0x00000000, },
-{R, 1, "", PCH_PP_STATUS, 0x00000000, },
-{M, 1, "[drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle"},
-{M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:00000000"},
-{R, 2, "", PCH_PP_STATUS, 0x00000000, },
-{R, 1, "", PCH_PP_CONTROL, 0x00000000, },
-{W, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
-{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
-{M, 1, "[drm:ironlake_edp_panel_vdd_on], R PCH_PP_CONTROL:abcd0008"},
-{R, 2, "", PCH_PP_STATUS, 0x00000000, },
-{M, 1, "[drm:ironlake_edp_panel_vdd_on], eDP was not running"},
-{R, 1, "", PCH_PP_STATUS, 0x00000000, },
-{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
-{R, 1, "", PCH_PP_STATUS, 0x00000000, },
-{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
-{R, 1, "", DPA_AUX_CH_CTL, 0x014300c8, },
-{W, 1, "", DPA_AUX_CH_DATA1, 0x9000000e, },
-{W, 1, "", DPA_AUX_CH_CTL, 0xd24500c8, },
-{R, 2, "", DPA_AUX_CH_CTL, 0x814500c8,  100},
-{R, 1, "", DPA_AUX_CH_CTL, 0x807500c8,  100},
-{R, 1, "", DPA_AUX_CH_CTL, 0x810500c8,  100},
-{R, 1, "", DPA_AUX_CH_CTL, 0x410500c8, },
-{W, 1, "", DPA_AUX_CH_CTL, 0x530500c8, },
-{R, 1, "", DPA_AUX_CH_DATA1, 0x00110a84, },
-{R, 1, "", DPA_AUX_CH_DATA2, 0x41000001, },
-{R, 1, "", DPA_AUX_CH_DATA3, 0xc0020000, },
-{R, 1, "", DPA_AUX_CH_DATA4, 0x001f0000, },
-{M, 1, "[drm:intel_dp_i2c_init], i2c_init DPDDC-A"},
-{R, 1, "", PCH_PP_STATUS, 0x00000000, },
-{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
-{R, 1, "", PCH_PP_STATUS, 0x00000000, },
-{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
-{R, 1, "", DPA_AUX_CH_CTL, 0x010500c8, },
-{W, 1, "", DPA_AUX_CH_DATA1, 0x40000000, },
-{W, 1, "", DPA_AUX_CH_CTL, 0xd23500c8, },
-{R, 2, "", DPA_AUX_CH_CTL, 0x810500c8,  100},
-{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, },
-{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, },
-{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000, },
-{R, 1, "", PCH_PP_STATUS, 0x00000000, },
-{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
-{R, 1, "", PCH_PP_STATUS, 0x00000000, },
-{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
-{R, 1, "", DPA_AUX_CH_CTL, 0x001500c8, },
-{W, 1, "", DPA_AUX_CH_DATA1, 0x00000000, },
-{W, 1, "", DPA_AUX_CH_CTL, 0xd23500c8, },
-{R, 2, "", DPA_AUX_CH_CTL, 0x801500c8,  100},
-{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, },
-{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, },
-{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000, },
-{M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1"},
-{R, 1, "", BLC_PWM_CPU_CTL, 0x000010ce, },
-{M, 1, "[drm:intel_panel_get_backlight], get backlight PWM = 4302"},
-{M, 1, "[drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f"},
-{M, 1, "[drm:intel_dp_i2c_aux_ch], aux_ch failed -110"},
-{M, 1,
-"[drm:ironlake_init_pch_refclk], has_panel 1 has_lvds 0 has_pch_edp 0"
-    "has_cpu_edp 1 has_ck505 0"},
-{R, 1, "", PCH_DREF_CONTROL, 0x00000000, },
-{M, 1, "[drm:ironlake_init_pch_refclk], Using SSC on panel"},
-{W, 1, "", PCH_DREF_CONTROL, 0x00001402, },
-{R, 1, "", PCH_DREF_CONTROL, 0x00001402,  200},
-{M, 1, "[drm:ironlake_init_pch_refclk], Using SSC on eDP"},
-{W, 1, "", PCH_DREF_CONTROL, 0x00005402, },
-{R, 1, "", PCH_DREF_CONTROL, 0x00005402,  200},
-{W, 1, "", ILK_DSPCLK_GATE, 0x10000000, },
-{W, 1, "", WM3_LP_ILK, 0x00000000, },
-{W, 1, "", WM2_LP_ILK, 0x00000000, },
-{W, 1, "", WM1_LP_ILK, 0x00000000, },
-{W, 1, "", 0x9404, 0x00002000, },
-{W, 1, "", ILK_DSPCLK_GATE, 0x10000000, },
-{W, 1, "", IVB_CHICKEN3, 0x00000024, },
-{W, 1, "", 0x7010, 0x04000400, },
-{W, 1, "", 0xb01c, 0x3c4fff8c, },
-{W, 1, "", 0xb030, 0x20000000, },
-{R, 1, "", 0x9030, 0x00000000, },
-{W, 1, "", 0x9030, 0x00000800, },
-{R, 1, "", _DSPACNTR, 0x00000000, },
-{W, 1, "", _DSPACNTR, 0x00004000, },
-{R, 1, "", _DSPAADDR, 0x00000000, },
-{W, 1, "", _DSPAADDR, 0x00000000, },
-{R, 1, "", _DSPASIZE+0xc, 0x00000000, },
-{W, 1, "", _DSPASIZE+0xc, 0x00000000, },
-{R, 1, "", _DSPBCNTR, 0x00000000, },
-{W, 1, "", _DSPBCNTR, 0x00004000, },
-{R, 1, "", _DSPBADDR, 0x00000000, },
-{W, 1, "", _DSPBADDR, 0x00000000, },
-{R, 1, "", _DSPBSURF, 0x00000000, },
-{W, 1, "", _DSPBSURF, 0x00000000, },
-{R, 1, "", _DVSACNTR, 0x00000000, },
-{W, 1, "", _DVSACNTR, 0x00004000, },
-{R, 1, "", _DVSALINOFF, 0x00000000, },
-{W, 1, "", _DVSALINOFF, 0x00000000, },
-{R, 1, "", _DVSASURF, 0x00000000, },
-{W, 1, "", _DVSASURF, 0x00000000, },
-{W, 1, "", SOUTH_DSPCLK_GATE_D, 0x20000000, },
-{R, 1, "", SOUTH_CHICKEN2, 0x00000000, },
-{W, 1, "", SOUTH_CHICKEN2, 0x00000001, },
-{W, 1, "", _TRANSA_CHICKEN2, 0x80000000, },
-{W, 1, "", _TRANSB_CHICKEN2, 0x80000000, },
-/* to here, it works ok  with v0 */
-//{V, 7,},
-{M, 1, "[drm:drm_edid_to_eld], ELD:no CEA Extension found"},
-{M, 1, "[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:6:eDP-1]"
-    "probed modes :"},
-{M, 1, "[drm:drm_mode_debug_printmodeline],"
-"Modeline 0:\"2560x1700\" 60 285250 2560 2608 2640 2720 1700 1703 1713 1749"
-"0x48 0xa"},
-{M, 1, "[drm:drm_setup_crtcs], "},
-{M, 1, "[drm:drm_enable_connectors], connector 6 enabled? yes"},
-{M, 1, "[drm:drm_setup_crtcs], picking CRTCs for 8192x8192 config"},
-{M, 1, "[drm:drm_setup_crtcs], desired mode 2560x1700 set on crtc 3"},
-{M, 1, "[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:6:eDP-1]"},
-{M, 1, "[drm:intel_dp_detect], DPCD:110a8441000001c0"},
-{M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on"},
-//{V, 7,},
-{M, 1, "[drm:intel_dp_detect], DPCD:110a8441000001c0"},
-{M, 1, "[drm:drm_enable_connectors], connector 6 enabled? yes"},
-{M, 1, "[drm:intel_get_load_detect_pipe], [CONNECTOR:6:eDP-1],"
-"[ENCODER:7:TMDS-7]"},
-{M, 1, "[drm:intel_dp_mode_fixup], Display port link bw 0a lane count 4"
-"clock 270000"},
-{M, 1, "[drm:drm_crtc_helper_set_mode], [CRTC:3]"},
-{R, 1, "", PCH_PP_STATUS, 0x00000000, },
-{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
-{R, 1, "", PCH_PP_STATUS, 0x00000000, },
-{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
-{R, 1, "", DPA_AUX_CH_CTL, 0x001500c8, },
-{W, 1, "", DPA_AUX_CH_DATA1, 0x80060000, },
-{W, 1, "", DPA_AUX_CH_DATA2, 0x01000000, },
-{W, 1, "", DPA_AUX_CH_CTL, 0xd25500c8, },
-{R, 2, "", DPA_AUX_CH_CTL, 0x801500c8,  100},
-{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, },
-{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, },
-{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000, },
-{R, 1, "", 0x64000, 0x0000001c, },
-{M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1"},
-#if 0
-/* I hope we never try to use this. It is left here as a documentation thing. */
-/* SCALING HACK */
-/* these were determined by reading registers.
- * They should stretch the display.
- * They don't.
- * From u-boot? After vbios?
- */
-{V, 7, },
-{M, 1, "Turning on panel fitter (must be done before power cycle)"},
-{W, 1, "Enabled,PIPEA,Hardcoded edge enhance", _PFA_CTL_1,    0x80800000, },
-/* status: can't ever set vscale.
- * Which may be why we get no display at all if we try. */
-{W, 1, "stretch", _PFA_VSCALE,   /*0x00004000*/0xffffffff, },
-{W, 1, "stretch", _PFA_HSCALE,   /*0x00004000*/0xffffffff, },
-{W, 1, "2560x1700", _PFA_WIN_SZ,   0x0a0006a4, },
-//{W, 1, "2560x1700", _PFA_WIN_SZ,   0x05000352, },
-{W, 1, "@[0,0]", _PFA_WIN_POS,  0x00000000, },
-{R, 1, "Vstretch", _PFA_VSCALE,   0x00004000, },
-{R, 1, "Hstretch", _PFA_HSCALE,   0x00004000, },
-{R, 1, "2560x1700", _PFA_WIN_SZ,   0x0a0006a4, },
-{R, 1, "@[0,0]", _PFA_WIN_POS,  0x00000000, },
-{R, 1, "Enabled,PIPEA,Hardcoded edge enhance", _PFA_CTL_1,    0x80800000, },
-{V,0,},
-/* END SCALING HACK */
-#endif
-{R, 2, "", PCH_DP_D, 0x00000004, },
-{R, 1, "", _PIPEACONF, 0x00000000, },
-{W, 1, "", _PIPEACONF, 0x00000040, },
-{R, 1, "", _PIPEACONF, 0x00000040, },
-{M, 1, "[drm:ironlake_crtc_mode_set], Mode for pipe 0:"},
-{M, 1, "[drm:drm_mode_debug_printmodeline],"
-"Modeline 0:\"2560x1700\" 60 285250 2560 2608 2640 2720 1700 1703 1713 1749"
-" 0x48 0xa"},
-{W, 1, "", _TRANSA_DATA_M1, 0x00000000, },
-{W, 1, "", _TRANSA_DATA_N1, 0x00000000, },
-{W, 1, "", _TRANSA_DP_LINK_M1, 0x00000000, },
-{W, 1, "", _TRANSA_DP_LINK_N1, 0x00000000, },
-{W, 1, "", _PCH_FPA1, 0x00020e08, },
-{W, 1, "", _VSYNCSHIFT_A, 0x00000000, },
-{W, 1, "", _HTOTAL_A, 0x0a9f09ff, },
-{W, 1, "", _HBLANK_A, 0x0a9f09ff, },
-{W, 1, "", _HSYNC_A, 0x0a4f0a2f, },
-{W, 1, "", _VTOTAL_A, 0x06d406a3, },
-{W, 1, "", _VBLANK_A, 0x06d406a3, },
-{W, 1, "", _VSYNC_A, 0x06b006a6, },
-{W, 1, "", _PIPEASRC, 0x09ff06a3, },
-{W, 1, "", _PIPEA_DATA_M1, 0x7e4e58a4, },
-{W, 1, "", _PIPEA_DATA_N1, 0x0083d600, },
-{W, 1, "", _PIPEA_LINK_M1, 0x00045a42, },
-{W, 1, "", _PIPEA_LINK_N1, 0x00041eb0, },
-{M, 1, "[drm:ironlake_set_pll_edp], eDP PLL enable for clock 270000"},
-{R, 1, "", 0x64000, 0x0000001c, },
-{W, 1, "", 0x64000, 0x0000001c, },
-{R, 1, "", 0x64000, 0x0000001c,  500},
-{W, 1, "", _PIPEACONF, 0x00000050, },
-{R, 1, "", _PIPEACONF, 0x00000050, },
-{R, 1, "", _PIPEASTAT, 0x00000000, },
-{W, 1, "", _PIPEASTAT, 0x00000002, },
-{R, 4562, "", _PIPEASTAT, 0x00000000, },
-{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out"},
-{W, 1, "", _DSPACNTR, 0x40000000, },
-{R, 2, "", _DSPACNTR, 0x40000000, },
-{W, 1, "", _DSPACNTR, 0x58004000, },
-{M, 1, "[drm:ironlake_update_plane], Writing base 00000000 00000000 0 0 10240"},
-{W, 1, "", _DSPASTRIDE, 0x00002800, },
-{W, 1, "", _DSPASIZE+0xc, 0x00000000, },
-{W, 1, "", _DSPACNTR+0x24, 0x00000000, },
-{W, 1, "", _DSPAADDR, 0x00000000, },
-{R, 1, "", _DSPACNTR, 0x58004000, },
-{R, 1, "", 0x145d10, 0x2010040c, },
-{R, 1, "", WM0_PIPEA_ILK, 0x00783818, },
-{W, 1, "", WM0_PIPEA_ILK, 0x00183806, },
-{M, 1, "[drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 24,"
-"cursor:6"},
-{W, 1, "", WM3_LP_ILK, 0x00000000, },
-{W, 1, "", WM2_LP_ILK, 0x00000000, },
-{W, 1, "", WM1_LP_ILK, 0x00000000, },
-{R, 1, "", 0x145d10, 0x2010040c, },
-{M, 1, "[drm:ironlake_check_srwm], watermark 1:display plane 38, fbc lines 3,"
-"cursor 6"},
-{R, 1, "", 0x145d10, 0x2010040c, },
-{W, 1, "", WM1_LP_ILK, 0x84302606, },
-{R, 1, "", 0x145d10, 0x2010040c, },
-{M, 1,"[drm:ironlake_check_srwm], watermark 2:display plane 145, fbc lines 3,"
-    "cursor 6"},
-{R, 1, "", 0x145d10, 0x2010040c, },
-{W, 1, "", WM2_LP_ILK, 0x90309106, },
-{R, 1, "", 0x145d10, 0x2010040c, },
-{M, 1, "[drm:ironlake_check_srwm], watermark 3:display plane 288, fbc lines 4,"
-    "cursor 10"},
-{R, 1, "", 0x145d10, 0x2010040c, },
-{W, 1, "", WM3_LP_ILK, 0xa041200a, },
-{M, 1, "[drm:drm_crtc_helper_set_mode], [ENCODER:7:TMDS-7]"
-    "set [MODE:0:2560x1700]"},
-{M, 1, "[drm:ironlake_edp_pll_on], "},
-{R, 1, "", 0x64000, 0x0000001c, },
-{W, 1, "", 0x64000, 0x0000401c, },
-{R, 1, "", 0x64000, 0x0000401c,  200},
-{R, 1, "", 0x64000, 0x0000401c, },
-{R, 1, "", 0x145d10, 0x2010040c, },
-{R, 1, "", WM0_PIPEA_ILK, 0x00183806, },
-{W, 1, "", WM0_PIPEA_ILK, 0x00183806, },
-{M, 1, "[drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 24,"
-"cursor:6"},
-{W, 1, "", WM3_LP_ILK, 0x00000000, },
-{W, 1, "", WM2_LP_ILK, 0x00000000, },
-{W, 1, "", WM1_LP_ILK, 0x00000000, },
-{R, 1, "", 0x145d10, 0x2010040c, },
-{M, 1, "[drm:ironlake_check_srwm], watermark 1:display plane 38, fbc lines 3,"
-    "cursor 6"},
-{R, 1, "", 0x145d10, 0x2010040c, },
-{W, 1, "", WM1_LP_ILK, 0x84302606, },
-{R, 1, "", 0x145d10, 0x2010040c, },
-{M, 1, "[drm:ironlake_check_srwm], watermark 2:display plane 145, fbc lines 3,"
-    "cursor 6"},
-{R, 1, "", 0x145d10, 0x2010040c, },
-{W, 1, "", WM2_LP_ILK, 0x90309106, },
-{R, 1, "", 0x145d10, 0x2010040c, },
-{M, 1, "[drm:ironlake_check_srwm], watermark 3:display plane 288, fbc lines 4,"
-    "cursor 10"},
-{R, 1, "", 0x145d10, 0x2010040c, },
-{W, 1, "", WM3_LP_ILK, 0xa041200a, },
-{R, 1, "", _FDI_TXA_CTL, 0x00040000, },
-{W, 1, "", _FDI_TXA_CTL, 0x00040000, },
-{R, 1, "", _FDI_TXA_CTL, 0x00040000, },
-{R, 1, "", _FDI_RXA_CTL, 0x00000040, },
-{R, 1, "", _PIPEACONF, 0x00000050, },
-{W, 1, "", _FDI_RXA_CTL, 0x00020040, },
-{R, 1, "", _FDI_RXA_CTL, 0x00020040,  100},
-{R, 1, "", SOUTH_CHICKEN1, 0x00000000, },
-{W, 2, "", SOUTH_CHICKEN1, 0x00000000, },
-{R, 1, "", SOUTH_CHICKEN1, 0x00000000, },
-{R, 1, "", _FDI_TXA_CTL, 0x00040000, },
-{W, 1, "", _FDI_TXA_CTL, 0x00040000, },
-{R, 1, "", _FDI_RXA_CTL, 0x00020040, },
-{R, 1, "", _PIPEACONF, 0x00000050, },
-{W, 1, "", _FDI_RXA_CTL, 0x00020040, },
-{R, 1, "", _FDI_RXA_CTL, 0x00020040,  100},
-{P, 1, "Set palette", },
-{R, 1, "", _PIPEACONF, 0x00000050, },
-{W, 1, "", _PIPEACONF, 0x80000050, },
-{R, 1, "", _PIPEASTAT, 0x00000000, },
-{W, 1, "", _PIPEASTAT, 0x00000002, },
-{R, 4533, "", _PIPEASTAT, 0x00000000, },
-{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out"},
-{R, 1, "", _PIPEACONF, 0xc0000050, },
-{R, 1, "", _DSPACNTR, 0x58004000, },
-{W, 1, "", _DSPACNTR, 0xd8004000, },
-{R, 1, "", _DSPAADDR, 0x00000000, },
-{W, 1, "", _DSPAADDR, 0x00000000, },
-{R, 1, "", _DSPASIZE+0xc, 0x00000000, },
-{W, 1, "", _DSPASIZE+0xc, 0x00000000, },
-{R, 1, "", _PIPEASTAT, 0x00000000, },
-{W, 1, "", _PIPEASTAT, 0x00000002, },
-{R, 4392, "", _PIPEASTAT, 0x00000000, },
-{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out"},
-{M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on"},
-{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
-{M, 1, "[drm:ironlake_edp_panel_on], Turn eDP power on"},
-{R, 1, "", PCH_PP_STATUS, 0x00000000, },
-{M, 1, "[drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle"},
-{M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:abcd0008"},
-{R, 2, "", PCH_PP_STATUS, 0x00000000, },
-{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
-{W, 1, "", PCH_PP_CONTROL, 0xabcd000b, },
-{R, 1, "", PCH_PP_CONTROL, 0xabcd000b, },
-{M, 1, "[drm:ironlake_wait_panel_on], Wait for panel power on"},
-{M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:abcd000b"},
-{R, 4, "", PCH_PP_STATUS, 0x0000000a, },
-{R, 16983, "", PCH_PP_STATUS, 0x9000000a, },
-{R, 17839, "", PCH_PP_STATUS, 0x90000009, },
-{R, 1, "", PCH_PP_STATUS, 0x80000008, },
-//{V, 7,},
-{M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1"},
-{R, 2, "", PCH_PP_CONTROL, 0xabcd000b, },
-{W, 1, "", PCH_PP_CONTROL, 0xabcd0003, },
-{R, 1, "", PCH_PP_CONTROL, 0xabcd0003, },
-{M, 1, "[drm:ironlake_panel_vdd_off_sync], R PCH_PP_CONTROL:abcd0003"},
-{R, 1, "", PCH_PP_STATUS, 0x80000008, },
-{W, 1, "", 0x64000, 0x8e1c4104, },
-{R, 1, "", 0x64000, 0x8e1c4104, },
-{R, 2, "", PCH_PP_STATUS, 0x80000008, },
-{R, 1, "", 0x64000, 0x8cdc4104, },
-{M, 1, "[drm:intel_dp_link_down], "},
-{W, 1, "", 0x64000, 0x8e1c0004, },
-{R, 1, "", 0x64000, 0x8e1c0004,  100},
-{W, 1, "", 0x64000, 0x8e1c0204, },
-{R, 1, "", 0x64000, 0x8e1c0204, },
-{W, 1, "", 0x64000, 0x0e1c0304, },
-{R, 2, "", 0x64000, 0x0e1c0304, },
-{R, 2, "", PCH_PP_STATUS, 0x80000008, },
-{R, 1, "", DPA_AUX_CH_CTL, 0x007500c8, },
-{W, 1, "", DPA_AUX_CH_DATA1, 0x80010008, },
-{W, 1, "", DPA_AUX_CH_DATA2, 0x0a840000, },
-{W, 1, "", DPA_AUX_CH_DATA3, 0x00000000, },
-{W, 1, "", DPA_AUX_CH_DATA4, 0x01000000, },
-{W, 1, "", DPA_AUX_CH_CTL, 0xd2d500c8, },
-{R, 3, "", DPA_AUX_CH_CTL, 0x807500c8,  100},
-{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, },
-{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, },
-{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000, },
-{W, 1, "", 0x64000, 0x891c4004, },
-{R, 1, "", 0x64000, 0x891c4004, },
-{R, 2, "", PCH_PP_STATUS, 0x80000008, },
-{R, 1, "", DPA_AUX_CH_CTL, 0x001500c8, },
-{W, 1, "", DPA_AUX_CH_DATA1, 0x80010200, },
-{W, 1, "", DPA_AUX_CH_DATA2, 0x21000000, },
-{W, 1, "", DPA_AUX_CH_CTL, 0xd25500c8, },
-{R, 2, "", DPA_AUX_CH_CTL, 0x801500c8,  100},
-{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, },
-{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, },
-{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000, },
-{R, 2, "", PCH_PP_STATUS, 0x80000008, },
-{R, 1, "", DPA_AUX_CH_CTL, 0x001500c8, },
-{W, 1, "", DPA_AUX_CH_DATA1, 0x80010303, },
-{W, 1, "", DPA_AUX_CH_DATA2, 0x00000000, },
-{W, 1, "", DPA_AUX_CH_CTL, 0xd28500c8, },
-{R, 3, "", DPA_AUX_CH_CTL, 0x801500c8,  100},
-{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, },
-{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, },
-{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000,  100},
-{R, 2, "", PCH_PP_STATUS, 0x80000008, },
-{R, 1, "", DPA_AUX_CH_CTL, 0x001500c8, },
-{W, 1, "", DPA_AUX_CH_DATA1, 0x90020205, },
-{W, 1, "", DPA_AUX_CH_CTL, 0xd24500c8, },
-{R, 2, "", DPA_AUX_CH_CTL, 0x801500c8,  100},
-{R, 1, "", DPA_AUX_CH_CTL, 0x804500c8,  100},
-{R, 1, "", DPA_AUX_CH_CTL, 0x407500c8, },
-{W, 1, "", DPA_AUX_CH_CTL, 0x527500c8, },
-{R, 1, "", DPA_AUX_CH_DATA1, 0x00111180, },
-{R, 1, "", DPA_AUX_CH_DATA2, 0x02000000, },
-{M, 1, "[drm:intel_dp_start_link_train], clock recovery OK"},
-{W, 1, "", 0x64000, 0x891c4104, },
-{R, 1, "", 0x64000, 0x891c4104, },
-{R, 2, "", PCH_PP_STATUS, 0x80000008, },
-{R, 1, "", DPA_AUX_CH_CTL, 0x007500c8, },
-{W, 1, "", DPA_AUX_CH_DATA1, 0x80010200, },
-{W, 1, "", DPA_AUX_CH_DATA2, 0x22000000, },
-{W, 1, "", DPA_AUX_CH_CTL, 0xd25500c8, },
-{R, 2, "", DPA_AUX_CH_CTL, 0x807500c8,  100},
-{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, },
-{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, },
-{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000, },
-{R, 2, "", PCH_PP_STATUS, 0x80000008, },
-{R, 1, "", DPA_AUX_CH_CTL, 0x001500c8, },
-{W, 1, "", DPA_AUX_CH_DATA1, 0x80010303, },
-{W, 1, "", DPA_AUX_CH_DATA2, 0x00000000, },
-{W, 1, "", DPA_AUX_CH_CTL, 0xd28500c8, },
-{R, 2, "", DPA_AUX_CH_CTL, 0x801500c8,  100},
-{R, 1, "", DPA_AUX_CH_CTL, 0x800500c8,  100},
-{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, },
-{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, },
-{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000,  400},
-{R, 2, "", PCH_PP_STATUS, 0x80000008, },
-{R, 1, "", DPA_AUX_CH_CTL, 0x001500c8, },
-{W, 1, "", DPA_AUX_CH_DATA1, 0x90020205, },
-{W, 1, "", DPA_AUX_CH_CTL, 0xd24500c8, },
-{R, 2, "", DPA_AUX_CH_CTL, 0x801500c8,  100},
-{R, 1, "", DPA_AUX_CH_CTL, 0x804500c8,  100},
-{R, 1, "", DPA_AUX_CH_CTL, 0x407500c8, },
-{W, 1, "", DPA_AUX_CH_CTL, 0x527500c8, },
-{R, 1, "", DPA_AUX_CH_DATA1, 0x00777781, },
-{R, 1, "", DPA_AUX_CH_DATA2, 0x02000000, },
-{W, 1, "", 0x64000, 0x891c4304, },
-{R, 1, "", 0x64000, 0x891c4304, },
-{R, 2, "", PCH_PP_STATUS, 0x80000008, },
-{R, 1, "", DPA_AUX_CH_CTL, 0x007500c8, },
-{W, 1, "", DPA_AUX_CH_DATA1, 0x80010200, },
-{W, 1, "", DPA_AUX_CH_DATA2, 0x00000000, },
-{W, 1, "", DPA_AUX_CH_CTL, 0xd25500c8, },
-{R, 2, "", DPA_AUX_CH_CTL, 0x807500c8,  100},
-{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, },
-{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, },
-{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000, },
-{M, 1, "[drm:ironlake_edp_backlight_on], "},
-{R, 1, "", PCH_PP_CONTROL, 0xabcd0003, },
-{W, 1, "", PCH_PP_CONTROL, 0xabcd0007, },
-{R, 1, "", PCH_PP_CONTROL, 0xabcd0007, },
-{R, 1, "", _PIPEADSL, 0x00000633,  500},
-{R, 1, "", _PIPEADSL, 0x00000652, },
-{R, 1, "", _PIPEASTAT, 0x00000000, },
-{W, 1, "", _PIPEASTAT, 0x00000002, },
-{R, 5085, "", _PIPEASTAT, 0x00000000, },
-{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out"},
-{M, 1, "[drm:intel_dp_mode_fixup], Display port link bw 0a lane count 4"
-    "clock 270000"},
-{M, 1, "[drm:drm_crtc_helper_set_mode], [CRTC:3]"},
-{0,},
-};
+{V, 0},
+{W, 1, "", PCH_GMBUS0, 0x00000000, 0},
+{R, 1, "", PP_ON_DELAYS, ( /* T2 */ 0x0 << 16) | ( /* T5 */ 0x0 << 0) | 0x00000000, 0},
+{R, 1, "", PP_OFF_DELAYS, ( /* T3 */ 0x0 << 16) | ( /* Tx */ 0x0 << 0) | 0x00000000, 0},
+{W, 1, "", PP_ON_DELAYS, ( /* T2 */ 0x190 << 16) | ( /* T5 */ 0x7d0 << 0) | 0x019007d0, 0},
+{W, 1, "", PP_OFF_DELAYS, ( /* T3 */ 0x15e << 16) | ( /* Tx */ 0x7d0 << 0) | 0x015e07d0, 0},
+{M, 1, "[drm:intel_detect_pch], Found PatherPoint PCH", 0x0, 0xcf8e64, 0},
+{M, 1, "[drm:i915_load_modeset_init], failed to find VBIOS tables", 0x0, 0xcf8e64, 0},
+{R, 50, "", FORCEWAKE_MT_ACK, 0x00000001, 10},
+{W, 1, "", FORCEWAKE_MT, 0x00010001, 0},
+{R, 1, "", FORCEWAKE_MT, 0x00010001, 0},
+{R, 1, "", FORCEWAKE_MT_ACK, 0x00000001, 0},
+{R, 1, "", 0x13805c, 0x40000000, 0},
+{R, 1, "", 0xa180, 0x84100020, 0},
+{W, 1, "", FORCEWAKE_MT, 0x00010000, 0},
+{R, 1, "", 0x120000, 0x00000000, 0},
+{M, 1, "[drm:intel_init_display], Using MT version of forcewake", 0x0, 0xcf8e64, 0},
+{R, 1, "", 0x145d10, 0x2010040c, 0},
+{M, 1, "[drm:intel_modeset_init], 3 display pipes available.", 0x0, 0xcf8e64, 0},
+{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
+{W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
+{R, 1, "", _PIPEBCONF, 0x00000000, 0},
+{W, 1, "", _PIPEBCONF, 0x00000000, 0},
+{R, 1, "", 0x72008, 0x00000000, 0},
+{W, 1, "", 0x72008, 0x00000000, 0},
+{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
+{W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
+{R, 1, "", _PIPEBCONF, 0x00000000, 0},
+{W, 1, "", _PIPEBCONF, 0x00000000, 0},
+{R, 1, "", 0x72008, 0x00000000, 0},
+{W, 1, "", 0x72008, 0x00000000, 0},
+{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
+{W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
+{R, 1, "", _PIPEBCONF, 0x00000000, 0},
+{W, 1, "", _PIPEBCONF, 0x00000000, 0},
+{R, 1, "", 0x72008, 0x00000000, 0},
+{W, 1, "", 0x72008, 0x00000000, 300},
+{W, 1, "", CPU_VGACNTRL, 0x80000000, 0},
+{R, 1, "", CPU_VGACNTRL, 0x80000000, 0},
+{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0},
+{R, 1, "", PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_DPA | ( /* PANEL_POWER_UP_DELAY */ 0x7d0 << 16) | ( /* PANEL_LIGHT_ON_DELAY */ 0x7d0 << 0) | 0x47d007d0, 0},
+{R, 1, "", PCH_PP_OFF_DELAYS, ( /* PANEL_POWER_DOWN_DELAY */ 0x1f4 << 16) | ( /* PANEL_LIGHT_OFF_DELAY */ 0x7d0 << 0) | 0x01f407d0, 0},
+{R, 1, "", PCH_PP_DIVISOR, 0x00186906, 0},
+{M, 1, "[drm:intel_dp_init], cur t1_t3 2000 t8 2000 t9 2000 t10 500t11_t12 6000", 0x0, 0xcf8e64, 0},
+{M, 1, "[drm:intel_dp_init], vbt t1_t3 0 t8 0 t9 0 t10 0 t11_t12 0", 0x0, 0xcf8e64, 0},
+{M, 1, "[drm:intel_dp_init], panel power up delay 200,power down" "delay 50, power cycle delay 600", 0x0, 0xcf8e64, 0},
+{M, 1, "[drm:intel_dp_init], backlight on delay 200, off delay 200", 0x0, 0xcf8e64, 0},
+{M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on", 0x0, 0xcf8e64, 0},
+{R, 1, "", PCH_PP_CONTROL, 0x00000000, 0},
+{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
+{M, 1, "[drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle", 0x0, 0xcf8e64, 0},
+{M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:00000000", 0x0, 0xcf8e64, 0},
+{R, 2, "", PCH_PP_STATUS, 0x00000000, 0},
+{R, 1, "", PCH_PP_CONTROL, 0x00000000, 0},
+{W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
+{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
+{M, 1, "[drm:ironlake_edp_panel_vdd_on], R PCH_PP_CONTROL:abcd0008", 0x0, 0xcf8e64, 0},
+{R, 2, "", PCH_PP_STATUS, 0x00000000, 0},
+{M, 1, "[drm:ironlake_edp_panel_vdd_on], eDP was not running", 0x0, 0xcf8e64, 0},
+{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
+{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
+{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
+{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
+{M, 1, "[drm:intel_dp_i2c_init], i2c_init DPDDC-A", 0x0, 0x00000000, 0},
+{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
+{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
+{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
+{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
+{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
+{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
+{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
+{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
+{I,},
+{M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1", 0x0, 0x00000000, 0},
+{R, 1, "", BLC_PWM_CPU_CTL, 0x000010ce, 0},
+{M, 1, "[drm:intel_panel_get_backlight], get backlight PWM = 4302", 0x0, 0xcf8e64, 0},
+{M, 1, "[drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f", 0x0, 0xcf8e64, 0},
+{M, 1, "[drm:intel_dp_i2c_aux_ch], aux_ch failed -110", 0x0, 0xcf8e64, 0},
+{M, 1, "[drm:ironlake_init_pch_refclk], has_panel 1 has_lvds 0 " "has_pch_edp 0has_cpu_edp 1 has_ck505 0", 0x0, 0xcf8e64, 0},
+{R, 1, "", PCH_DREF_CONTROL, 0x00000000, 0},
+{M, 1, "[drm:ironlake_init_pch_refclk], Using SSC on panel", 0x0, 0xcf8e64, 0},
+{W, 1, "", PCH_DREF_CONTROL, DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00001402, 0},
+{R, 1, "", PCH_DREF_CONTROL, DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00001402, 200},
+{M, 1, "[drm:ironlake_init_pch_refclk], Using SSC on eDP", 0x0, 0xcf8e64, 0},
+{W, 1, "", PCH_DREF_CONTROL, DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD | DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00005402, 0},
+{R, 1, "", PCH_DREF_CONTROL, DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD | DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00005402, 200},
+{W, 1, "", ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE | 0x10000000, 0},
+{W, 1, "", WM3_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
+{W, 1, "", WM2_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
+{W, 1, "", WM1_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
+{W, 1, "", 0x9404, 0x00002000, 0},
+{W, 1, "", ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE | 0x10000000, 0},
+{W, 1, "", IVB_CHICKEN3, 0x00000024, 0},
+{W, 1, "", GEN7_COMMON_SLICE_CHICKEN1, 0x04000400, 0},
+{W, 1, "", 0xb01c, 0x3c4fff8c, 0},
+{W, 1, "", GEN7_L3_CHICKEN_MODE_REGISTER, 0x20000000, 0},
+{R, 1, "", GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 0x00000000, 0},
+{W, 1, "", GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 0x00000800, 0},
+{R, 1, "", _DSPACNTR, ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x00000000, 0},
+{W, 1, "", _DSPACNTR, ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */  | 0x00004000, 0},
+{R, 1, "", _DSPAADDR, 0x00000000, 0},
+{W, 1, "", _DSPAADDR, 0x00000000, 0},
+{R, 1, "", _DSPASIZE + 0xc, 0x00000000, 0},
+{W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0},
+{R, 1, "", _DSPBCNTR, 0x00000000, 0},
+{W, 1, "", _DSPBCNTR, 0x00004000, 0},
+{R, 1, "", _DSPBADDR, 0x00000000, 0},
+{W, 1, "", _DSPBADDR, 0x00000000, 0},
+{R, 1, "", _DSPBSURF, 0x00000000, 0},
+{W, 1, "", _DSPBSURF, 0x00000000, 0},
+{R, 1, "", _DVSACNTR, 0x00000000, 0},
+{W, 1, "", _DVSACNTR, DVS_TRICKLE_FEED_DISABLE | 0x00004000, 0},
+{R, 1, "", _DVSALINOFF, 0x00000000, 0},
+{W, 1, "", _DVSALINOFF, 0x00000000, 0},
+{R, 1, "", _DVSASURF, 0x00000000, 0},
+{W, 1, "", _DVSASURF, 0x00000000, 0},
+{W, 1, "", SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | 0x20000000, 0},
+{R, 1, "", SOUTH_CHICKEN2, 0x00000000, 0},
+{W, 1, "", SOUTH_CHICKEN2, DPLS_EDP_PPS_FIX_DIS | 0x00000001, 0},
+{W, 1, "", _TRANSA_CHICKEN2, 0x80000000, 0},
+{W, 1, "", _TRANSB_CHICKEN2, TRANS_AUTOTRAIN_GEN_STALL_DIS | 0x80000000, 0},
+{M, 1, "[drm:drm_edid_to_eld], ELD:no CEA Extension found", 0x0, 0xcf8e64, 0},
+{M, 1, "[drm:drm_helper_probe_single_connector_modes], " "[CONNECTOR:6:eDP-1]probed modes :", 0x0, 0xcf8e64, 0},
+{M, 1, "[drm:drm_mode_debug_printmodeline],Modeline 0:\"2560x1700\" " "60 285250 2560 2608 2640 2720 1700 1703 1713 17490x48 0xa", 0x0, 0xcf8e64, 0},
+{M, 1, "[drm:drm_setup_crtcs], ", 0x0, 0xcf8e64, 0},
+{M, 1, "[drm:drm_enable_connectors], connector 6 enabled? yes", 0x0, 0xcf8e64, 0},
+{M, 1, "[drm:drm_setup_crtcs], picking CRTCs for 8192x8192 config", 0x0, 0xcf8e64, 0},
+{M, 1, "[drm:drm_setup_crtcs], desired mode 2560x1700 set on crtc 3", 0x0, 0xcf8e64, 0},
+{M, 1, "[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:6:eDP-1]", 0x0, 0xcf8e64, 0},
+{M, 1, "[drm:intel_dp_detect], DPCD:110a8441000001c0", 0x0, 0xcf8e64, 0},
+{M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on", 0x0, 0xcf8e64, 0},
+{M, 1, "[drm:intel_dp_detect], DPCD:110a8441000001c0", 0x0, 0xcf8e64, 0},
+{M, 1, "[drm:drm_enable_connectors], connector 6 enabled? yes", 0x0, 0xcf8e64, 0},
+{M, 1, "[drm:intel_get_load_detect_pipe], [CONNECTOR:6:eDP-1],[ENCODER:7:TMDS-7]", 0x0, 0xcf8e64, 0},
+{M, 1, "[drm:intel_dp_mode_fixup], Display port link bw 0a lane count 4clock 270000", 0x0, 0xcf8e64, 0},
+{M, 1, "[drm:drm_crtc_helper_set_mode], [CRTC:3]", 0x0, 0xcf8e64, 0},
+{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
+{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
+{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
+{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
+{I,},
+{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0},
+{M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1", 0x0, 0xcf8e64, 0},
+{R, 2, "", PCH_DP_D, 0x00000004, 0},
+{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
+{W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_TYPE_SP | 0x00000040, 0},
+{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_TYPE_SP | 0x00000040, 0},
+{M, 1, "[drm:ironlake_crtc_mode_set], Mode for pipe 0:", 0x0, 0xcf8e64, 0},
+{M, 1, "[drm:drm_mode_debug_printmodeline],Modeline 0:\"2560x1700\" " "60 285250 2560 2608 2640 2720 1700 1703 1713 1749 0x48 0xa", 0x0, 0xcf8e64, 0},
+{W, 1, "", _TRANSA_DATA_M1, 0x00000000, 0},
+{W, 1, "", _TRANSA_DATA_N1, 0x00000000, 0},
+{W, 1, "", _TRANSA_DP_LINK_M1, 0x00000000, 0},
+{W, 1, "", _TRANSA_DP_LINK_N1, 0x00000000, 0},
+{W, 1, "", _PCH_FPA1, 0x00020e08, 0},
+{W, 1, "", _VSYNCSHIFT_A, 0x00000000, 0},
+{W, 1, "", _HTOTAL_A, 0x0a9f09ff, 0},
+{W, 1, "", _HBLANK_A, 0x0a9f09ff, 0},
+{W, 1, "", _HSYNC_A, 0x0a4f0a2f, 0},
+{W, 1, "", _VTOTAL_A, 0x06d406a3, 0},
+{W, 1, "", _VBLANK_A, 0x06d406a3, 0},
+{W, 1, "", _VSYNC_A, 0x06b006a6, 0},
+{W, 1, "", _PIPEASRC, 0x09ff06a3, 0},
+{W, 1, "", _PIPEA_DATA_M1, 0x7e4e58a4, 0},
+{W, 1, "", _PIPEA_DATA_N1, 0x0083d600, 0},
+{W, 1, "", _PIPEA_LINK_M1, 0x00045a42, 0},
+{W, 1, "", _PIPEA_LINK_N1, 0x00041eb0, 0},
+{M, 1, "[drm:ironlake_set_pll_edp], eDP PLL enable for clock 270000", 0x0, 0xcf8e64, 0},
+{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0},
+{W, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0},
+{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 500},
+{W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0},
+{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0},
+{R, 1, "", _PIPEASTAT, 0x00000000, 0},
+{W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0},
+{R, 4562, "", _PIPEASTAT, 0x00000000, 0},
+{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0},
+{W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x40000000, 0},
+{R, 2, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x40000000, 0},
+{W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_32BPP_NO_ALPHA & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */  | 0x58004000, 0},
+{M, 1, "[drm:ironlake_update_plane], Writing base 00000000 00000000 0 0 10240", 0x0, 0xcf8e64, 0},
+{W, 1, "", _DSPASTRIDE, 0x00002800, 0},
+{W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0},
+{W, 1, "", _DSPACNTR + 0x24, 0x00000000, 0},
+{W, 1, "", _DSPAADDR, 0x00000000, 0},
+{R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_32BPP_NO_ALPHA & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */  | 0x58004000, 0},
+{R, 1, "", 0x145d10, 0x2010040c, 0},
+{R, 1, "", WM0_PIPEA_ILK, 0x00783818, 0},
+{W, 1, "", WM0_PIPEA_ILK, 0x00183806, 0},
+{M, 1, "[drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 24,cursor:6", 0x0, 0xcf8e64, 0},
+{W, 1, "", WM3_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
+{W, 1, "", WM2_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
+{W, 1, "", WM1_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
+{R, 1, "", 0x145d10, 0x2010040c, 0},
+{M, 1, "[drm:ironlake_check_srwm], watermark 1:display plane 38, fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0},
+{R, 1, "", 0x145d10, 0x2010040c, 0},
+{W, 1, "", WM1_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x4 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) | ( /* WMx_LP_SR */ 0x26 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x84302606, 0},
+{R, 1, "", 0x145d10, 0x2010040c, 0},
+{M, 1, "[drm:ironlake_check_srwm], watermark 2:display plane 145, " "fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0},
+{R, 1, "", 0x145d10, 0x2010040c, 0},
+{W, 1, "", WM2_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x10 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) | ( /* WMx_LP_SR */ 0x91 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x90309106, 0},
+{R, 1, "", 0x145d10, 0x2010040c, 0},
+{M, 1, "[drm:ironlake_check_srwm], watermark 3:display plane " "288, fbc lines 4,cursor 10", 0x0, 0xcf8e64, 0},
+{R, 1, "", 0x145d10, 0x2010040c, 0},
+{W, 1, "", WM3_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x20 << 24) | ( /* WMx_LP_FBC */ 0x4 << 20) | ( /* WMx_LP_SR */ 0x120 << 8) | ( /* WMx_LP_CURSOR */ 0xa << 0) | 0xa041200a, 0},
+{M, 1, "[drm:drm_crtc_helper_set_mode], [ENCODER:7:TMDS-7]set [MODE:0:2560x1700]", 0x0, 0xcf8e64, 0},
+{M, 1, "[drm:ironlake_edp_pll_on], ", 0x0, 0xcf8e64, 0},
+{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0},
+{W, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000401c, 0},
+{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000401c, 200},
+{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000401c, 0},
+{R, 1, "", 0x145d10, 0x2010040c, 0},
+{R, 1, "", WM0_PIPEA_ILK, 0x00183806, 0},
+{W, 1, "", WM0_PIPEA_ILK, 0x00183806, 0},
+{M, 1, "[drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 24,cursor:6", 0x0, 0xcf8e64, 0},
+{W, 1, "", WM3_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
+{W, 1, "", WM2_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
+{W, 1, "", WM1_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
+{R, 1, "", 0x145d10, 0x2010040c, 0},
+{M, 1, "[drm:ironlake_check_srwm], watermark 1:display plane 38, fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0},
+{R, 1, "", 0x145d10, 0x2010040c, 0},
+{W, 1, "", WM1_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x4 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) |( /* WMx_LP_SR */ 0x26 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x84302606, 0},
+{R, 1, "", 0x145d10, 0x2010040c, 0},
+{M, 1, "[drm:ironlake_check_srwm], watermark 2:display plane 145, " "fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0},
+{R, 1, "", 0x145d10, 0x2010040c, 0},
+{W, 1, "", WM2_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x10 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) |( /* WMx_LP_SR */ 0x91 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x90309106, 0},
+{R, 1, "", 0x145d10, 0x2010040c, 0},
+{M, 1, "[drm:ironlake_check_srwm], watermark 3:display plane 288, " "fbc lines 4,cursor 10", 0x0, 0xcf8e64, 0},
+{R, 1, "", 0x145d10, 0x2010040c, 0},
+{W, 1, "", WM3_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x20 << 24) | ( /* WMx_LP_FBC */ 0x4 << 20) |( /* WMx_LP_SR */ 0x120 << 8) | ( /* WMx_LP_CURSOR */ 0xa << 0) | 0xa041200a, 0},
+{R, 1, "", _FDI_TXA_CTL, 0x00040000, 0},
+{W, 1, "", _FDI_TXA_CTL, 0x00040000, 0},
+{R, 1, "", _FDI_TXA_CTL, 0x00040000, 0},
+{R, 1, "", _FDI_RXA_CTL, 0x00000040, 0},
+{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0},
+{W, 1, "", _FDI_RXA_CTL, 0x00020040, 0},
+{R, 1, "", _FDI_RXA_CTL, 0x00020040, 100},
+{R, 1, "", SOUTH_CHICKEN1, 0x00000000, 0},
+{W, 2, "", SOUTH_CHICKEN1, 0x00000000, 0},
+{R, 1, "", SOUTH_CHICKEN1, 0x00000000, 0},
+{R, 1, "", _FDI_TXA_CTL, 0x00040000, 0},
+{W, 1, "", _FDI_TXA_CTL, 0x00040000, 0},
+{R, 1, "", _FDI_RXA_CTL, 0x00020040, 0},
+{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0},
+{W, 1, "", _FDI_RXA_CTL, 0x00020040, 0},
+{R, 1, "", _FDI_RXA_CTL, 0x00020040, 100},
+{P, 1, "Set Palette"},
+{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0},
+{W, 1, "", _PIPEACONF, PIPECONF_ENABLE | ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x80000050, 0},
+{R, 1, "", _PIPEASTAT, 0x00000000, 0},
+{W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0},
+{R, 4533, "", _PIPEASTAT, 0x00000000, 0},
+{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0},
+{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | PIPECONF_DOUBLE_WIDE | ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP |0xc0000050, 0},
+{R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_32BPP_NO_ALPHA & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */  | 0x58004000, 0},
+{W, 1, "", _DSPACNTR, DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE | (DISPPLANE_32BPP_NO_ALPHA & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */  | 0xd8004000, 0},
+{R, 1, "", _DSPAADDR, 0x00000000, 0},
+{W, 1, "", _DSPAADDR, 0x00000000, 0},
+{R, 1, "", _DSPASIZE + 0xc, 0x00000000, 0},
+{W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0},
+{R, 1, "", _PIPEASTAT, 0x00000000, 0},
+{W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0},
+{R, 4392, "", _PIPEASTAT, 0x00000000, 0},
+{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0},
+{M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on", 0x0, 0xcf8e64, 0},
+{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
+{M, 1, "[drm:ironlake_edp_panel_on], Turn eDP power on", 0x0, 0xcf8e64, 0},
+{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
+{M, 1, "[drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle", 0x0, 0xcf8e64, 0},
+{M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:abcd0008", 0x0, 0xcf8e64, 0},
+{R, 2, "", PCH_PP_STATUS, 0x00000000, 0},
+{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
+{W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd000b, 0},
+{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd000b, 0},
+{M, 1, "[drm:ironlake_wait_panel_on], Wait for panel power on", 0x0, 0xcf8e64, 0},
+{M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:abcd000b", 0x0, 0xcf8e64, 0},
+{R, 4, "", PCH_PP_STATUS, /*undocbit3 | undocbit1 | */ 0x0000000a, 0},
+{R, 16983, "", PCH_PP_STATUS, PP_ON | PP_SEQUENCE_POWER_UP | /*undocbit3 | undocbit1 | */ 0x9000000a, 0},
+{R, 17839, "", PCH_PP_STATUS, PP_ON | PP_SEQUENCE_POWER_UP | /*undocbit3 | undocbit0 | */ 0x90000009, 0},
+{R, 1, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
+{M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1", 0x0, 0xcf8e64, 0},
+{R, 2, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd000b, 0},
+{W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0003, 0},
+{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0003, 0},
+{M, 1, "[drm:ironlake_panel_vdd_off_sync], R PCH_PP_CONTROL:abcd0003", 0x0, 0xcf8e64, 0},
+{R, 1, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
+{W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x8e1c4104, 0},
+{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x8e1c4104, 0},
+{R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
+{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | (DP_PRE_EMPHASIS_9_5 & 0xc00000) | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x8cdc4104, 0},
+{M, 1, "[drm:intel_dp_link_down], ", 0x0, 0xcf8e64, 0},
+{W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0004, 0},
+{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0004, 100},
+{W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_IDLE_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0204, 0},
+{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_IDLE_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0204, 0},
+{W, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x0e1c0304, 0},
+{R, 2, "", DP_A, DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x0e1c0304, 0},
+{R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
+{I,},
+{W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4004, 0},
+{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4004, 0},
+{R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
+{I,},
+{R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
+{I,},
+{R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
+{I,},
+{M, 1, "[drm:intel_dp_start_link_train], clock recovery OK", 0x0, 0x00000000, 0},
+{W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4104, 0},
+{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4104, 0},
+{R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0},
+{I,},
+{R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0},
+{I,},
+{R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0},
+{I,},
+{W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4304, 0},
+{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4304, 0},
+{R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0},
+{I,},
+{M, 1, "[drm:ironlake_edp_backlight_on], ", 0x0, 0x00000000, 0},
+{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0003, 0},
+{W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0007, 0},
+{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0007, 0},
+{R, 1, "", _PIPEADSL, 0x00000633, 500},
+{R, 1, "", _PIPEADSL, 0x00000652, 0},
+{R, 1, "", _PIPEASTAT, 0x00000000, 0},
+{W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0},
+{R, 5085, "", _PIPEASTAT, 0x00000000, 0},
+{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0},
+{M, 1, "[drm:intel_dp_mode_fixup], Display port link bw 0a lane count 4clock 270000", 0x0, 0xcf8e64, 0},
+{M, 1, "[drm:drm_crtc_helper_set_mode], [CRTC:3]", 0x0, 0xcf8e64, 0},
+{I, 0, "(null)", 0x0, 0xcf8e64, 0}, };
+
+int niodefs = sizeof (iodefs) / sizeof (iodefs[0]);