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| author | Aaron Durbin <adurbin@chromium.org> | 2013-05-23 15:57:46 -0500 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-11-25 23:37:57 +0100 |
| commit | b1c25e74af0a7b1cb4aae0fc9ab8147ee9d14907 (patch) | |
| tree | dc46deac7f5c9c16e64ac7c569eaf854a7dd4b8a /src/mainboard/google/link/mainboard.c | |
| parent | 5290f71569d1bf8b6fa80d34f4b176407082fec8 (diff) | |
| download | coreboot-b1c25e74af0a7b1cb4aae0fc9ab8147ee9d14907.tar.xz | |
haswell: update pei_data data structure
Update and use the new pei_data data structure. Now that the
reference code is fixed it's possible to properly disable/enable
the USB2 and USB3 ports correctly.
Change-Id: I075c646e7574be354420b6e59507e8917a97d0f0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56594
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4185
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/google/link/mainboard.c')
0 files changed, 0 insertions, 0 deletions