summaryrefslogtreecommitdiff
path: root/src/mainboard/google/link
diff options
context:
space:
mode:
authorAngel Pons <th3fanbus@gmail.com>2020-09-02 19:17:30 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-09-08 05:27:08 +0000
commitdc0c08100124278efc9ed91952378b01905c45b6 (patch)
tree561ef4cde49e51bebf9804bf3558b099cb2ebe20 /src/mainboard/google/link
parentd04957970cc55743db3d896b3975570b42f05d95 (diff)
downloadcoreboot-dc0c08100124278efc9ed91952378b01905c45b6.tar.xz
nb/intel/sandybridge: Use an enum for `gpu_panel_port_select`
All boards currently have backlight on either LVDS or eDP. Change-Id: I878bc7f1ff75a2b82b9556e855aff1d4d03e0268 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/google/link')
-rw-r--r--src/mainboard/google/link/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb
index 477cd47c32..6ce51a3961 100644
--- a/src/mainboard/google/link/devicetree.cb
+++ b/src/mainboard/google/link/devicetree.cb
@@ -6,7 +6,7 @@ chip northbridge/intel/sandybridge
register "gpu_dp_d_hotplug" = "0x06"
# Enable Panel as eDP and configure power delays
- register "gpu_panel_port_select" = "1" # eDP_A
+ register "gpu_panel_port_select" = "PANEL_PORT_DP_A"
register "gpu_panel_power_cycle_delay" = "6" # 500ms
register "gpu_panel_power_up_delay" = "2000" # 200ms
register "gpu_panel_power_down_delay" = "500" # 50ms