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| author | Martin Roth <martinroth@google.com> | 2019-08-29 12:32:53 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-10-03 15:29:53 +0000 |
| commit | dcf86e0cffde76aee45372849b710c2aac5fffa8 (patch) | |
| tree | 5cc392aa964784710818e9b1227de8b5a40852f5 /src/mainboard/google/link | |
| parent | d8b150f0d578a5182ce11698906776c0d1d448e9 (diff) | |
| download | coreboot-dcf86e0cffde76aee45372849b710c2aac5fffa8.tar.xz | |
mb/[google/intel]/*: Specify Chrome EC bus - LPC or ESPI
Previously all boards using eSPI for the Chrome EC just called it
LPC as the code for the chrome EC is the same between the two
busses.
I'm adding a new Kconfig symbol to specify eSPI, so switch the
boards that actually use eSPI to that symbol and add the LPC
symbol to all the others.
The EC_GOOGLE_CHROMEEC_LPC symbol will no longer default
to enabled for x86 platforms, so one symbol or the other needs to be
specified for each platform.
BUG=b:140055300
TEST=Build tested only.
Change-Id: Icf242ca2b7d8b1470feda4e44b47a2cdc20680f2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/link')
| -rw-r--r-- | src/mainboard/google/link/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index b7421900dc..12c5ffeb38 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS select SOUTHBRIDGE_INTEL_C216 select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_LPC select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME |