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authorMatt DeVillier <matt.devillier@gmail.com>2015-10-20 19:36:09 -0500
committerMartin Roth <martinroth@google.com>2016-05-31 21:15:27 +0200
commita87fcabd2efe49c8035b76146401e190a0ea6593 (patch)
tree9cbb2fcef19484ebf5c96aa6211468c25d09a1d2 /src/mainboard/google/ninja/chromeos.fmd
parent4acb0e774220c0705a71689b6620c976297d417c (diff)
downloadcoreboot-a87fcabd2efe49c8035b76146401e190a0ea6593.tar.xz
google/ninja: Upstream AOpen Chromebox Commerical
Migrate google/ninja (AOpen Chromebox Commerical) from Chromium tree to upstream, using google/rambi as a reference. original source: branch firmware-ninja-5216.383.B commit 582a393 [Ninja, Sumo: Add SPD source for Hynix H5TC4G63CFR-PBA] TEST=built and booted Linux on ninja with full functionality blobs required for working image: VGA BIOS (vgabios.bin) firmware descriptor (ifd.bin) Intel ME firmware (me.bin) MRC (mrc.elf) external reference code (refcode.elf) Change-Id: I0f1892c24c08fa2d53185b2cf8b6f5a9001b2397 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/14950 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/ninja/chromeos.fmd')
-rw-r--r--src/mainboard/google/ninja/chromeos.fmd38
1 files changed, 38 insertions, 0 deletions
diff --git a/src/mainboard/google/ninja/chromeos.fmd b/src/mainboard/google/ninja/chromeos.fmd
new file mode 100644
index 0000000000..113fba6e6f
--- /dev/null
+++ b/src/mainboard/google/ninja/chromeos.fmd
@@ -0,0 +1,38 @@
+FLASH@0xff800000 0x800000 {
+ SI_ALL@0x0 0x200000 {
+ SI_DESC@0x0 0x1000
+ SI_ME@0x1000 0x1ff000
+ }
+ SI_BIOS@0x200000 0x600000 {
+ RW_SECTION_A@0x0 0xf0000 {
+ VBLOCK_A@0x0 0x10000
+ FW_MAIN_A(CBFS)@0x10000 0xdffc0
+ RW_FWID_A@0xeffc0 0x40
+ }
+ RW_SECTION_B@0xf0000 0xf0000 {
+ VBLOCK_B@0x0 0x10000
+ FW_MAIN_B(CBFS)@0x10000 0xdffc0
+ RW_FWID_B@0xeffc0 0x40
+ }
+ RW_MRC_CACHE@0x1e0000 0x10000
+ RW_ELOG@0x1f0000 0x4000
+ RW_SHARED@0x1f4000 0x4000 {
+ SHARED_DATA@0x0 0x2000
+ VBLOCK_DEV@0x2000 0x2000
+ }
+ RW_VPD@0x1f8000 0x2000
+ RW_UNUSED@0x1fa000 0x6000
+ RW_LEGACY(CBFS)@0x200000 0x200000
+ WP_RO@0x400000 0x200000 {
+ RO_VPD@0x0 0x4000
+ RO_UNUSED@0x4000 0xc000
+ RO_SECTION@0x10000 0x1f0000 {
+ FMAP@0x0 0x800
+ RO_FRID@0x800 0x40
+ RO_FRID_PAD@0x840 0x7c0
+ GBB@0x1000 0xef000
+ COREBOOT(CBFS)@0xf0000 0x100000
+ }
+ }
+ }
+}