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authorTom Warren <twarren@nvidia.com>2014-01-23 13:37:50 -0700
committerMarc Jones <marc.jones@se-eng.com>2014-10-22 03:56:49 +0200
commit64982c5002994270e1fc010cc8d2119c20f62184 (patch)
tree025c601d766107d6bde7a7ce5c7755a0e59be9d2 /src/mainboard/google/nyan
parentb3f08c61f15970ef3d9e197b02d6dedb8b2c5830 (diff)
downloadcoreboot-64982c5002994270e1fc010cc8d2119c20f62184.tar.xz
tegra/nyan*: sdram updates
nyan_big: Add 204MHz BCT for bringup, use 1.2V for VDD_CPU Reviewed-on: https://chromium-review.googlesource.com/183939 (cherry picked from commit a6df76afb5342b805baca749abb8265e15748dc1) nyan_big: Add initial 792MHz BCT Reviewed-on: https://chromium-review.googlesource.com/183975 (cherry picked from commit 61d0122fdce6dc9479666bb0a5bc079c6389f78a) nyan_big: use RAM_CODE[3:2] for ram code Reviewed-on: https://chromium-review.googlesource.com/184076 (cherry picked from commit 35e5c5e473f871cdc897473a31586afbececd716) tegra124: support tri-state Board Id Reviewed-on: https://chromium-review.googlesource.com/183855 (cherry picked from commit 1a9d1bd73aa2cd0c36203b247976ad0d00a360e4) nyan*: Fix SPI pinmux configuration Reviewed-on: https://chromium-review.googlesource.com/184281 (cherry picked from commit ac4106b673c285af66d72392bd4a8522aba98489) nyan_big: Add 4GB 204/792MHz BCTs Reviewed-on: https://chromium-review.googlesource.com/184159 (cherry picked from commit 5ff002d09f8db0543b58962f6c0d24627fb0937e) tegra124: Add function for obtaining DRAM size via MC regs Reviewed-on: https://chromium-review.googlesource.com/184535 (cherry picked from commit d4580c46de649903a266a99eb11c9126ba385b48) tegra124/nyan*: Obtain DRAM size dynamically Reviewed-on: https://chromium-review.googlesource.com/184431 (cherry picked from commit a7db71744771decc04cf1966efba70bf4897cfa3) tegra124: Rearrange iRAM layout to allow more space for romstage Reviewed-on: https://chromium-review.googlesource.com/184240 (cherry picked from commit 6bdaabbc068146a4516c724b71d31bb777dabcfc) tegra124: Fix MemoryType field name in SDRAM parameters. Reviewed-on: https://chromium-review.googlesource.com/185113 (cherry picked from commit 9caccd1e86a8c683402fab87d9f3a49b87496e97) nyan_big: Initialize SDRAM without BootROM. Reviewed-on: https://chromium-review.googlesource.com/183624 (cherry picked from commit a1cbc00aa80ec1ea52e833a8e31c8e4b27160e70) tegra124: move FB_SIZE_MB to a more appropriate location Reviewed-on: https://chromium-review.googlesource.com/184930 (cherry picked from commit ddea486fd4410394417c4e59039d46a324918bdc) nyan: Initialize SDRAM without BootROM. Reviewed-on: https://chromium-review.googlesource.com/185114 (cherry picked from commit 1ff51b580b28553919f91b11b443251b048cf26b) tegra124: Save SDRAM parameters to PMC registers for LP0 Reviewed-on: https://chromium-review.googlesource.com/182928 (cherry picked from commit 7476b4bd0ecdc312476cce871d22f57915a0bd86) tegra124: Rewrite SDRAM parameter saving code to be more efficient Reviewed-on: https://chromium-review.googlesource.com/184388 (cherry picked from commit 25084bd0407624e4b2ff82388c32af1198c501a6) nyan: Slightly change the way SDRAM parameter files are set up Reviewed-on: https://chromium-review.googlesource.com/185286 (cherry picked from commit a31887b804f23e031c395113db582cd71f3d1b6d) Squashed 16 commits for SDRAM support on nyan and nyan_big. Change-Id: I07419985376277083d62400dd14fe8273f6d5ca8 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6949 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/mainboard/google/nyan')
-rw-r--r--src/mainboard/google/nyan/Kconfig18
-rw-r--r--src/mainboard/google/nyan/Makefile.inc1
-rw-r--r--src/mainboard/google/nyan/bct/Makefile.inc6
-rwxr-xr-xsrc/mainboard/google/nyan/bct/cfg2inc.sh34
-rw-r--r--src/mainboard/google/nyan/bct/sdram-792.cfg346
-rw-r--r--src/mainboard/google/nyan/bct/sdram-924.cfg346
-rw-r--r--src/mainboard/google/nyan/bct/sdram-hynix-2GB-792.inc311
-rw-r--r--src/mainboard/google/nyan/bct/sdram-hynix-2GB-924.inc311
-rw-r--r--src/mainboard/google/nyan/bct/sdram-unused.inc4
-rw-r--r--src/mainboard/google/nyan/bootblock.c18
-rw-r--r--src/mainboard/google/nyan/romstage.c22
-rw-r--r--src/mainboard/google/nyan/sdram_configs.c58
-rw-r--r--src/mainboard/google/nyan/sdram_configs.h28
13 files changed, 775 insertions, 728 deletions
diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig
index f0cef6a315..61a17b4718 100644
--- a/src/mainboard/google/nyan/Kconfig
+++ b/src/mainboard/google/nyan/Kconfig
@@ -39,10 +39,6 @@ config MAINBOARD_PART_NUMBER
string
default "Nyan"
-config DRAM_SIZE_MB
- int
- default 2048
-
config DRAM_DMA_START
hex
default 0x90000000
@@ -89,18 +85,4 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS
hex
default 1
-choice
- prompt "BCT sdram configuration"
- default NYAN_BCT_SDRAM_792
- help
- The SDRAM configuration to put in the BCT.
-
-config NYAN_BCT_SDRAM_792
- bool "792 MHz"
-
-config NYAN_BCT_SDRAM_924
- bool "924 MHz"
-
-endchoice
-
endif # BOARD_GOOGLE_NYAN
diff --git a/src/mainboard/google/nyan/Makefile.inc b/src/mainboard/google/nyan/Makefile.inc
index e612af3551..825b33e9d7 100644
--- a/src/mainboard/google/nyan/Makefile.inc
+++ b/src/mainboard/google/nyan/Makefile.inc
@@ -32,6 +32,7 @@ bootblock-y += bootblock.c
bootblock-y += pmic.c
romstage-y += romstage.c
+romstage-y += sdram_configs.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-y += mainboard.c
diff --git a/src/mainboard/google/nyan/bct/Makefile.inc b/src/mainboard/google/nyan/bct/Makefile.inc
index aacd89f210..32490eba01 100644
--- a/src/mainboard/google/nyan/bct/Makefile.inc
+++ b/src/mainboard/google/nyan/bct/Makefile.inc
@@ -20,5 +20,7 @@
bct-cfg-$(CONFIG_NYAN_BCT_CFG_EMMC) += emmc.cfg
bct-cfg-$(CONFIG_NYAN_BCT_CFG_SPI) += spi.cfg
bct-cfg-y += odmdata.cfg
-bct-cfg-$(CONFIG_NYAN_BCT_SDRAM_924) += sdram-924.cfg
-bct-cfg-$(CONFIG_NYAN_BCT_SDRAM_792) += sdram-792.cfg
+
+# Note when SDRAM config (sdram-*.cfg) files are changed, we have to regenerate
+# the include files (sdram-*.inc) by running "./cfg2inc.sh sdram-*.cfg".
+# TODO(hungte) Change cfg2inc.sh to NVIDIA's official tool in cbootimage.
diff --git a/src/mainboard/google/nyan/bct/cfg2inc.sh b/src/mainboard/google/nyan/bct/cfg2inc.sh
new file mode 100755
index 0000000000..6d0c7a8eaf
--- /dev/null
+++ b/src/mainboard/google/nyan/bct/cfg2inc.sh
@@ -0,0 +1,34 @@
+#!/bin/sh
+#
+# This file is part of the coreboot project.
+#
+# Copyright 2014 Google Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+
+bct_cfg2inc() {
+ local in_file="$1"
+ local out_file="$2"
+ echo "{ /* generated from ${in_file}; do not edit. */" >"${out_file}"
+ # Note currently we can only handle DDR3 type memory, even in C
+ # implementation.
+ sed "/^#.*$/d; s/^SDRAM.0./ /; s/;$/,/;" \
+ "${in_file}" >> "${out_file}"
+ echo "}," >>"${out_file}"
+}
+
+for file in $@; do
+ echo "Generating $file => ${file%cfg}inc..."
+ bct_cfg2inc "${file}" "${file%cfg}inc"
+done
diff --git a/src/mainboard/google/nyan/bct/sdram-792.cfg b/src/mainboard/google/nyan/bct/sdram-792.cfg
deleted file mode 100644
index d4d96600a5..0000000000
--- a/src/mainboard/google/nyan/bct/sdram-792.cfg
+++ /dev/null
@@ -1,346 +0,0 @@
-# CFG Version 07
-# Do not edit. Generated by gen_sdram_cfg V4.0.7. Command:
-# gen_sdram_cfg -i ddr3_256Mx16x4_H5TC4G63AFR_RDA.par 1.262 -dram_board_cfg 10 -fly_by_time_ps 1650
-# -b PM358/PM358_792MHz_emc_reg.txt -o PM358_Hynix_2GB_H5TC4G63AFR_RDA_792Mhz.cfg
-# Parameter file: ddr3_256Mx16x4_H5TC4G63AFR_RDA.par, tck = 1.26 ns (792.39 MHz)
-# bkv file: PM358/PM358_792MHz_emc_reg.txt
-SDRAM[0].MemoryType = NvBootMemoryType_Ddr3;
-SDRAM[0].PllMInputDivider = 0x00000001;
-SDRAM[0].PllMFeedbackDivider = 0x00000042;
-SDRAM[0].PllMStableTime = 0x0000012c;
-SDRAM[0].PllMSetupControl = 0x00000000;
-SDRAM[0].PllMSelectDiv2 = 0x00000000;
-SDRAM[0].PllMPDLshiftPh45 = 0x00000001;
-SDRAM[0].PllMPDLshiftPh90 = 0x00000001;
-SDRAM[0].PllMPDLshiftPh135 = 0x00000001;
-SDRAM[0].PllMKCP = 0x00000000;
-SDRAM[0].PllMKVCO = 0x00000000;
-SDRAM[0].EmcBctSpare0 = 0x00000000;
-SDRAM[0].EmcBctSpare1 = 0x00000000;
-SDRAM[0].EmcBctSpare2 = 0x00000000;
-SDRAM[0].EmcBctSpare3 = 0x00000000;
-SDRAM[0].EmcBctSpare4 = 0x00000000;
-SDRAM[0].EmcBctSpare5 = 0x00000000;
-SDRAM[0].EmcBctSpare6 = 0x00000000;
-SDRAM[0].EmcBctSpare7 = 0x00000000;
-SDRAM[0].EmcBctSpare8 = 0x00000000;
-SDRAM[0].EmcBctSpare9 = 0x00000000;
-SDRAM[0].EmcBctSpare10 = 0x00000000;
-SDRAM[0].EmcBctSpare11 = 0x00000000;
-SDRAM[0].EmcClockSource = 0x80000000;
-SDRAM[0].EmcAutoCalInterval = 0x001fffff;
-SDRAM[0].EmcAutoCalConfig = 0xa1430000;
-SDRAM[0].EmcAutoCalConfig2 = 0x00000000;
-SDRAM[0].EmcAutoCalConfig3 = 0x00000000;
-SDRAM[0].EmcAutoCalWait = 0x00000190;
-SDRAM[0].EmcAdrCfg = 0x00000000;
-SDRAM[0].EmcPinProgramWait = 0x00000001;
-SDRAM[0].EmcPinExtraWait = 0x00000000;
-SDRAM[0].EmcTimingControlWait = 0x00000000;
-SDRAM[0].EmcRc = 0x00000025;
-SDRAM[0].EmcRfc = 0x000000cd;
-SDRAM[0].EmcRfcSlr = 0x00000000;
-SDRAM[0].EmcRas = 0x00000019;
-SDRAM[0].EmcRp = 0x0000000a;
-SDRAM[0].EmcR2r = 0x00000000;
-SDRAM[0].EmcW2w = 0x00000000;
-SDRAM[0].EmcR2w = 0x00000007;
-SDRAM[0].EmcW2r = 0x0000000d;
-SDRAM[0].EmcR2p = 0x00000004;
-SDRAM[0].EmcW2p = 0x00000013;
-SDRAM[0].EmcRdRcd = 0x0000000a;
-SDRAM[0].EmcWrRcd = 0x0000000a;
-SDRAM[0].EmcRrd = 0x00000003;
-SDRAM[0].EmcRext = 0x00000002;
-SDRAM[0].EmcWext = 0x00000000;
-SDRAM[0].EmcWdv = 0x00000006;
-SDRAM[0].EmcWdvMask = 0x00000006;
-SDRAM[0].EmcQUse = 0x0000000b;
-SDRAM[0].EmcQuseWidth = 0x00000002;
-SDRAM[0].EmcIbdly = 0x00000000;
-SDRAM[0].EmcEInput = 0x00000003;
-SDRAM[0].EmcEInputDuration = 0x0000000c;
-SDRAM[0].EmcPutermExtra = 0x00090000;
-SDRAM[0].EmcPutermWidth = 0x00000004;
-SDRAM[0].EmcPutermAdj = 0x00000000;
-SDRAM[0].EmcCdbCntl1 = 0x00000000;
-SDRAM[0].EmcCdbCntl2 = 0x00000000;
-SDRAM[0].EmcCdbCntl3 = 0x00000000;
-SDRAM[0].EmcQRst = 0x00000002;
-SDRAM[0].EmcQSafe = 0x00000011;
-SDRAM[0].EmcRdv = 0x00000017;
-SDRAM[0].EmcRdvMask = 0x00000019;
-SDRAM[0].EmcQpop = 0x0000000f;
-SDRAM[0].EmcCtt = 0x00000000;
-SDRAM[0].EmcCttDuration = 0x00000004;
-SDRAM[0].EmcRefresh = 0x000017eb;
-SDRAM[0].EmcBurstRefreshNum = 0x00000000;
-SDRAM[0].EmcPreRefreshReqCnt = 0x000005fa;
-SDRAM[0].EmcPdEx2Wr = 0x00000003;
-SDRAM[0].EmcPdEx2Rd = 0x00000003;
-SDRAM[0].EmcPChg2Pden = 0x00000001;
-SDRAM[0].EmcAct2Pden = 0x00000000;
-SDRAM[0].EmcAr2Pden = 0x000000c7;
-SDRAM[0].EmcRw2Pden = 0x00000018;
-SDRAM[0].EmcTxsr = 0x000000d7;
-SDRAM[0].EmcTxsrDll = 0x00000200;
-SDRAM[0].EmcTcke = 0x00000005;
-SDRAM[0].EmcTckesr = 0x00000006;
-SDRAM[0].EmcTpd = 0x00000005;
-SDRAM[0].EmcTfaw = 0x0000001d;
-SDRAM[0].EmcTrpab = 0x00000000;
-SDRAM[0].EmcTClkStable = 0x00000008;
-SDRAM[0].EmcTClkStop = 0x00000008;
-SDRAM[0].EmcTRefBw = 0x0000182c;
-SDRAM[0].EmcFbioCfg5 = 0x104ab898;
-SDRAM[0].EmcFbioCfg6 = 0x00000002;
-SDRAM[0].EmcFbioSpare = 0x00000000;
-SDRAM[0].EmcCfgRsv = 0xff00ff00;
-SDRAM[0].EmcMrs = 0x80001d71;
-SDRAM[0].EmcEmrs = 0x80100002;
-SDRAM[0].EmcEmrs2 = 0x80200018;
-SDRAM[0].EmcEmrs3 = 0x80300000;
-SDRAM[0].EmcMrw1 = 0x00000000;
-SDRAM[0].EmcMrw2 = 0x00000000;
-SDRAM[0].EmcMrw3 = 0x00000000;
-SDRAM[0].EmcMrw4 = 0x00000000;
-SDRAM[0].EmcMrwExtra = 0x00000000;
-SDRAM[0].EmcWarmBootMrwExtra = 0x00000000;
-SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000;
-SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000;
-SDRAM[0].EmcMrwResetCommand = 0x00000000;
-SDRAM[0].EmcMrwResetNInitWait = 0x00000000;
-SDRAM[0].EmcMrsWaitCnt = 0x00f7000e;
-SDRAM[0].EmcMrsWaitCnt2 = 0x00f7000e;
-SDRAM[0].EmcCfg = 0x73300000;
-SDRAM[0].EmcCfg2 = 0x0000089d;
-SDRAM[0].EmcCfgPipe = 0x000040a0;
-SDRAM[0].EmcDbg = 0x01000c00;
-SDRAM[0].EmcCmdQ = 0x10004408;
-SDRAM[0].EmcMc2EmcQ = 0x06000404;
-SDRAM[0].EmcDynSelfRefControl = 0x80003025;
-SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001;
-SDRAM[0].EmcCfgDigDll = 0xe00701b1;
-SDRAM[0].EmcCfgDigDllPeriod = 0x00008000;
-SDRAM[0].EmcDevSelect = 0x00000002;
-SDRAM[0].EmcSelDpdCtrl = 0x00040000;
-SDRAM[0].EmcDllXformDqs0 = 0x00000008;
-SDRAM[0].EmcDllXformDqs1 = 0x00000008;
-SDRAM[0].EmcDllXformDqs2 = 0x00000008;
-SDRAM[0].EmcDllXformDqs3 = 0x00000008;
-SDRAM[0].EmcDllXformDqs4 = 0x00000008;
-SDRAM[0].EmcDllXformDqs5 = 0x00000008;
-SDRAM[0].EmcDllXformDqs6 = 0x00000008;
-SDRAM[0].EmcDllXformDqs7 = 0x00000008;
-SDRAM[0].EmcDllXformDqs8 = 0x00000008;
-SDRAM[0].EmcDllXformDqs9 = 0x00000008;
-SDRAM[0].EmcDllXformDqs10 = 0x00000008;
-SDRAM[0].EmcDllXformDqs11 = 0x00000008;
-SDRAM[0].EmcDllXformDqs12 = 0x00000008;
-SDRAM[0].EmcDllXformDqs13 = 0x00000008;
-SDRAM[0].EmcDllXformDqs14 = 0x00000008;
-SDRAM[0].EmcDllXformDqs15 = 0x00000008;
-SDRAM[0].EmcDllXformQUse0 = 0x00000000;
-SDRAM[0].EmcDllXformQUse1 = 0x00000000;
-SDRAM[0].EmcDllXformQUse2 = 0x00000000;
-SDRAM[0].EmcDllXformQUse3 = 0x00000000;
-SDRAM[0].EmcDllXformQUse4 = 0x00000000;
-SDRAM[0].EmcDllXformQUse5 = 0x00000000;
-SDRAM[0].EmcDllXformQUse6 = 0x00000000;
-SDRAM[0].EmcDllXformQUse7 = 0x00000000;
-SDRAM[0].EmcDllXformAddr0 = 0x0000000e;
-SDRAM[0].EmcDllXformAddr1 = 0x0000000e;
-SDRAM[0].EmcDllXformAddr2 = 0x00000000;
-SDRAM[0].EmcDllXformAddr3 = 0x0000000e;
-SDRAM[0].EmcDllXformAddr4 = 0x00000000;
-SDRAM[0].EmcDllXformAddr5 = 0x00000000;
-SDRAM[0].EmcDllXformQUse8 = 0x00000000;
-SDRAM[0].EmcDllXformQUse9 = 0x00000000;
-SDRAM[0].EmcDllXformQUse10 = 0x00000000;
-SDRAM[0].EmcDllXformQUse11 = 0x00000000;
-SDRAM[0].EmcDllXformQUse12 = 0x00000000;
-SDRAM[0].EmcDllXformQUse13 = 0x00000000;
-SDRAM[0].EmcDllXformQUse14 = 0x00000000;
-SDRAM[0].EmcDllXformQUse15 = 0x00000000;
-SDRAM[0].EmcDliTrimTxDqs0 = 0x00000000;
-SDRAM[0].EmcDliTrimTxDqs1 = 0x00000000;
-SDRAM[0].EmcDliTrimTxDqs2 = 0x00000000;
-SDRAM[0].EmcDliTrimTxDqs3 = 0x00000000;
-SDRAM[0].EmcDliTrimTxDqs4 = 0x00000000;
-SDRAM[0].EmcDliTrimTxDqs5 = 0x00000000;
-SDRAM[0].EmcDliTrimTxDqs6 = 0x00000000;
-SDRAM[0].EmcDliTrimTxDqs7 = 0x00000000;
-SDRAM[0].EmcDliTrimTxDqs8 = 0x00000000;
-SDRAM[0].EmcDliTrimTxDqs9 = 0x00000000;
-SDRAM[0].EmcDliTrimTxDqs10 = 0x00000000;
-SDRAM[0].EmcDliTrimTxDqs11 = 0x00000000;
-SDRAM[0].EmcDliTrimTxDqs12 = 0x00000000;
-SDRAM[0].EmcDliTrimTxDqs13 = 0x00000000;
-SDRAM[0].EmcDliTrimTxDqs14 = 0x00000000;
-SDRAM[0].EmcDliTrimTxDqs15 = 0x00000000;
-SDRAM[0].EmcDllXformDq0 = 0x0000000b;
-SDRAM[0].EmcDllXformDq1 = 0x0000000b;
-SDRAM[0].EmcDllXformDq2 = 0x0000000b;
-SDRAM[0].EmcDllXformDq3 = 0x0000000b;
-SDRAM[0].EmcDllXformDq4 = 0x0000000b;
-SDRAM[0].EmcDllXformDq5 = 0x0000000b;
-SDRAM[0].EmcDllXformDq6 = 0x0000000b;
-SDRAM[0].EmcDllXformDq7 = 0x0000000b;
-SDRAM[0].WarmBootWait = 0x00000002;
-SDRAM[0].EmcCttTermCtrl = 0x00000802;
-SDRAM[0].EmcOdtWrite = 0x00000000;
-SDRAM[0].EmcOdtRead = 0x00000000;
-SDRAM[0].EmcZcalInterval = 0x00020000;
-SDRAM[0].EmcZcalWaitCnt = 0x00000042;
-SDRAM[0].EmcZcalMrwCmd = 0x80000000;
-SDRAM[0].EmcMrsResetDll = 0x00000000;
-SDRAM[0].EmcZcalInitDev0 = 0x80000011;
-SDRAM[0].EmcZcalInitDev1 = 0x00000000;
-SDRAM[0].EmcZcalInitWait = 0x00000001;
-SDRAM[0].EmcZcalWarmColdBootEnables = 0x00000003;
-SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab;
-SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000000;
-SDRAM[0].EmcZcalWarmBootWait = 0x00000001;
-SDRAM[0].EmcMrsWarmBootEnable = 0x00000001;
-SDRAM[0].EmcMrsResetDllWait = 0x00000000;
-SDRAM[0].EmcMrsExtra = 0x80001d71;
-SDRAM[0].EmcWarmBootMrsExtra = 0x80100002;
-SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000;
-SDRAM[0].EmcMrsDdr2DllReset = 0x00000000;
-SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000;
-SDRAM[0].EmcDdr2Wait = 0x00000000;
-SDRAM[0].EmcClkenOverride = 0x00000000;
-SDRAM[0].McDisExtraSnapLevels = 0x00000000;
-SDRAM[0].EmcExtraRefreshNum = 0x00000002;
-SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000;
-SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000;
-SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003;
-SDRAM[0].PmcVddpSel = 0x00000002;
-SDRAM[0].PmcVddpSelWait = 0x00000002;
-SDRAM[0].PmcDdrPwr = 0x00000003;
-SDRAM[0].PmcDdrCfg = 0x00002002;
-SDRAM[0].PmcIoDpd3Req = 0x4fff2f97;
-SDRAM[0].PmcIoDpd3ReqWait = 0x00000000;
-SDRAM[0].PmcRegShort = 0x00000000;
-SDRAM[0].PmcNoIoPower = 0x00000000;
-SDRAM[0].PmcPorDpdCtrlWait = 0x00000000;
-SDRAM[0].EmcXm2CmdPadCtrl = 0x100002a0;
-SDRAM[0].EmcXm2CmdPadCtrl2 = 0x770c0000;
-SDRAM[0].EmcXm2CmdPadCtrl3 = 0x050c0000;
-SDRAM[0].EmcXm2CmdPadCtrl4 = 0x00000000;
-SDRAM[0].EmcXm2CmdPadCtrl5 = 0x00111111;
-SDRAM[0].EmcXm2DqsPadCtrl = 0x770c1414;
-SDRAM[0].EmcXm2DqsPadCtrl2 = 0x0020013d;
-SDRAM[0].EmcXm2DqsPadCtrl3 = 0x61861820;
-SDRAM[0].EmcXm2DqsPadCtrl4 = 0x00514514;
-SDRAM[0].EmcXm2DqsPadCtrl5 = 0x00514514;
-SDRAM[0].EmcXm2DqsPadCtrl6 = 0x61861800;
-SDRAM[0].EmcXm2DqPadCtrl = 0x770c2990;
-SDRAM[0].EmcXm2DqPadCtrl2 = 0x00000000;
-SDRAM[0].EmcXm2DqPadCtrl3 = 0x00000000;
-SDRAM[0].EmcXm2ClkPadCtrl = 0x77ffc085;
-SDRAM[0].EmcXm2ClkPadCtrl2 = 0x00000707;
-SDRAM[0].EmcXm2CompPadCtrl = 0x81f1f108;
-SDRAM[0].EmcXm2VttGenPadCtrl = 0x07070004;
-SDRAM[0].EmcXm2VttGenPadCtrl2 = 0x00000000;
-SDRAM[0].EmcXm2VttGenPadCtrl3 = 0x017fffff;
-SDRAM[0].EmcAcpdControl = 0x00000000;
-SDRAM[0].EmcSwizzleRank0ByteCfg = 0x00003120;
-SDRAM[0].EmcSwizzleRank0Byte0 = 0x25143067;
-SDRAM[0].EmcSwizzleRank0Byte1 = 0x45367102;
-SDRAM[0].EmcSwizzleRank0Byte2 = 0x47106253;
-SDRAM[0].EmcSwizzleRank0Byte3 = 0x04362175;
-SDRAM[0].EmcSwizzleRank1ByteCfg = 0x00003120;
-SDRAM[0].EmcSwizzleRank1Byte0 = 0x71546032;
-SDRAM[0].EmcSwizzleRank1Byte1 = 0x35104276;
-SDRAM[0].EmcSwizzleRank1Byte2 = 0x27043615;
-SDRAM[0].EmcSwizzleRank1Byte3 = 0x72306145;
-SDRAM[0].EmcDsrVttgenDrv = 0x0505003f;
-SDRAM[0].EmcTxdsrvttgen = 0x00000000;
-SDRAM[0].EmcBgbiasCtl0 = 0x00000000;
-SDRAM[0].McEmemAdrCfg = 0x00000000;
-SDRAM[0].McEmemAdrCfgDev0 = 0x00080303;
-SDRAM[0].McEmemAdrCfgDev1 = 0x00080303;
-SDRAM[0].McEmemAdrCfgBankMask0 = 0x00001248;
-SDRAM[0].McEmemAdrCfgBankMask1 = 0x00002490;
-SDRAM[0].McEmemAdrCfgBankMask2 = 0x00000920;
-SDRAM[0].McEmemAdrCfgBankSwizzle3 = 0x00000001;
-SDRAM[0].McEmemCfg = 0x00000800;
-SDRAM[0].McEmemArbCfg = 0x0e00000b;
-SDRAM[0].McEmemArbOutstandingReq = 0x80000040;
-SDRAM[0].McEmemArbTimingRcd = 0x00000004;
-SDRAM[0].McEmemArbTimingRp = 0x00000005;
-SDRAM[0].McEmemArbTimingRc = 0x00000013;
-SDRAM[0].McEmemArbTimingRas = 0x0000000c;
-SDRAM[0].McEmemArbTimingFaw = 0x0000000f;
-SDRAM[0].McEmemArbTimingRrd = 0x00000002;
-SDRAM[0].McEmemArbTimingRap2Pre = 0x00000003;
-SDRAM[0].McEmemArbTimingWap2Pre = 0x0000000c;
-SDRAM[0].McEmemArbTimingR2R = 0x00000002;
-SDRAM[0].McEmemArbTimingW2W = 0x00000002;
-SDRAM[0].McEmemArbTimingR2W = 0x00000005;
-SDRAM[0].McEmemArbTimingW2R = 0x00000008;
-SDRAM[0].McEmemArbDaTurns = 0x08050202;
-SDRAM[0].McEmemArbDaCovers = 0x00170e13;
-SDRAM[0].McEmemArbMisc0 = 0x736c2414;
-SDRAM[0].McEmemArbMisc1 = 0x70000f02;
-SDRAM[0].McEmemArbRing1Throttle = 0x001f0000;
-SDRAM[0].McEmemArbOverride = 0x10000000;
-SDRAM[0].McEmemArbOverride1 = 0x00000000;
-SDRAM[0].McEmemArbRsv = 0xff00ff00;
-SDRAM[0].McClkenOverride = 0x00000000;
-SDRAM[0].McStatControl = 0x00000000;
-SDRAM[0].McDisplaySnapRing = 0x00000003;
-SDRAM[0].McVideoProtectBom = 0xfff00000;
-SDRAM[0].McVideoProtectBomAdrHi = 0x00000000;
-SDRAM[0].McVideoProtectSizeMb = 0x00000000;
-SDRAM[0].McVideoProtectVprOverride = 0xe4bac743;
-SDRAM[0].McVideoProtectVprOverride1 = 0x00000013;
-SDRAM[0].McVideoProtectGpuOverride0 = 0x00000000;
-SDRAM[0].McVideoProtectGpuOverride1 = 0x00000000;
-SDRAM[0].McSecCarveoutBom = 0xfff00000;
-SDRAM[0].McSecCarveoutAdrHi = 0x00000000;
-SDRAM[0].McSecCarveoutSizeMb = 0x00000000;
-SDRAM[0].McVideoProtectWriteAccess = 0x00000000;
-SDRAM[0].McSecCarveoutProtectWriteAccess = 0x00000000;
-SDRAM[0].EmcCaTrainingEnable = 0x00000000;
-SDRAM[0].EmcCaTrainingTimingCntl1 = 0x1f7df7df;
-SDRAM[0].EmcCaTrainingTimingCntl2 = 0x0000001f;
-SDRAM[0].SwizzleRankByteEncode = 0x0000006f;
-SDRAM[0].BootRomPatchControl = 0x00000000;
-SDRAM[0].BootRomPatchData = 0x00000000;
-SDRAM[0].McMtsCarveoutBom = 0xfff00000;
-SDRAM[0].McMtsCarveoutAdrHi = 0x00000000;
-SDRAM[0].McMtsCarveoutSizeMb = 0x00000000;
-SDRAM[0].McMtsCarveoutRegCtrl = 0x00000000;
-#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x00000013;
-#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x0000017c;
-#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x00810038;
-#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x00810038;
-#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x0081003c;
-#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x00810090;
-#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x00810041;
-#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x00810090;
-#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x00810041;
-#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049;
-#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x00810080;
-#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x00810004;
-#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x00810004;
-#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080016;
-#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x00000081;
-#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x00810004;
-#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x00810019;
-#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x00810018;
-#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x00810024;
-#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x0081001c;
-#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x00000081;
-#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036;
-#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x00810081;
-#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036;
-#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x00810081;
-#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff;
-#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029;
-#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x00810081;
-#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x00810081;
-#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x00810065;
-#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x0081001c;
diff --git a/src/mainboard/google/nyan/bct/sdram-924.cfg b/src/mainboard/google/nyan/bct/sdram-924.cfg
deleted file mode 100644
index fa3271a160..0000000000
--- a/src/mainboard/google/nyan/bct/sdram-924.cfg
+++ /dev/null
@@ -1,346 +0,0 @@
-# CFG Version 11
-# Do not edit. Generated by gen_sdram_cfg V5.0.1. Command:
-# gen_sdram_cfg -i ddr3_256Mx16x4_H5TC4G63AFR_RDA.par 1.082 -dram_board_cfg 10 -fly_by_time_ps 1650
-# -b PM358/PM358_924MHz_emc_reg.txt -o PM358_Hynix_2GB_H5TC4G63AFR_RDA_924Mhz.cfg
-# Parameter file: ddr3_256Mx16x4_H5TC4G63AFR_RDA.par, tck = 1.08 ns (924.21 MHz)
-# bkv file: PM358/PM358_924MHz_emc_reg.txt
-SDRAM[0].MemoryType = NvBootMemoryType_Ddr3;
-SDRAM[0].PllMInputDivider = 0x00000001;
-SDRAM[0].PllMFeedbackDivider = 0x0000004d;
-SDRAM[0].PllMStableTime = 0x0000012c;
-SDRAM[0].PllMSetupControl = 0x00000000;
-SDRAM[0].PllMSelectDiv2 = 0x00000000;
-SDRAM[0].PllMPDLshiftPh45 = 0x00000001;
-SDRAM[0].PllMPDLshiftPh90 = 0x00000001;
-SDRAM[0].PllMPDLshiftPh135 = 0x00000001;
-SDRAM[0].PllMKCP = 0x00000000;
-SDRAM[0].PllMKVCO = 0x00000000;
-SDRAM[0].EmcBctSpare0 = 0x00000000;
-SDRAM[0].EmcBctSpare1 = 0x00000000;
-SDRAM[0].EmcBctSpare2 = 0x00000000;
-SDRAM[0].EmcBctSpare3 = 0x00000000;
-SDRAM[0].EmcBctSpare4 = 0x00000000;
-SDRAM[0].EmcBctSpare5 = 0x00000000;
-SDRAM[0].EmcBctSpare6 = 0x00000000;
-SDRAM[0].EmcBctSpare7 = 0x00000000;
-SDRAM[0].EmcBctSpare8 = 0x00000000;
-SDRAM[0].EmcBctSpare9 = 0x00000000;
-SDRAM[0].EmcBctSpare10 = 0x00000000;
-SDRAM[0].EmcBctSpare11 = 0x00000000;
-SDRAM[0].EmcClockSource = 0x80000000;
-SDRAM[0].EmcAutoCalInterval = 0x001fffff;
-SDRAM[0].EmcAutoCalConfig = 0xa1430404;
-SDRAM[0].EmcAutoCalConfig2 = 0x00000000;
-SDRAM[0].EmcAutoCalConfig3 = 0x00000000;
-SDRAM[0].EmcAutoCalWait = 0x00000190;
-SDRAM[0].EmcAdrCfg = 0x00000000;
-SDRAM[0].EmcPinProgramWait = 0x00000001;
-SDRAM[0].EmcPinExtraWait = 0x00000000;
-SDRAM[0].EmcTimingControlWait = 0x00000000;
-SDRAM[0].EmcRc = 0x0000002b;
-SDRAM[0].EmcRfc = 0x000000ef;
-SDRAM[0].EmcRfcSlr = 0x00000000;
-SDRAM[0].EmcRas = 0x0000001e;
-SDRAM[0].EmcRp = 0x0000000b;
-SDRAM[0].EmcR2r = 0x00000000;
-SDRAM[0].EmcW2w = 0x00000000;
-SDRAM[0].EmcR2w = 0x00000008;
-SDRAM[0].EmcW2r = 0x0000000f;
-SDRAM[0].EmcR2p = 0x00000005;
-SDRAM[0].EmcW2p = 0x00000016;
-SDRAM[0].EmcRdRcd = 0x0000000b;
-SDRAM[0].EmcWrRcd = 0x0000000b;
-SDRAM[0].EmcRrd = 0x00000004;
-SDRAM[0].EmcRext = 0x00000002;
-SDRAM[0].EmcWext = 0x00000000;
-SDRAM[0].EmcWdv = 0x00000006;
-SDRAM[0].EmcWdvMask = 0x00000006;
-SDRAM[0].EmcQUse = 0x0000000c;
-SDRAM[0].EmcQuseWidth = 0x00000002;
-SDRAM[0].EmcIbdly = 0x00000000;
-SDRAM[0].EmcEInput = 0x00000002;
-SDRAM[0].EmcEInputDuration = 0x0000000e;
-SDRAM[0].EmcPutermExtra = 0x000a0000;
-SDRAM[0].EmcPutermWidth = 0x00000004;
-SDRAM[0].EmcPutermAdj = 0x00000000;
-SDRAM[0].EmcCdbCntl1 = 0x00000000;
-SDRAM[0].EmcCdbCntl2 = 0x00000000;
-SDRAM[0].EmcCdbCntl3 = 0x00000000;
-SDRAM[0].EmcQRst = 0x00000001;
-SDRAM[0].EmcQSafe = 0x00000015;
-SDRAM[0].EmcRdv = 0x0000001b;
-SDRAM[0].EmcRdvMask = 0x0000001d;
-SDRAM[0].EmcQpop = 0x00000010;
-SDRAM[0].EmcCtt = 0x00000000;
-SDRAM[0].EmcCttDuration = 0x00000004;
-SDRAM[0].EmcRefresh = 0x00001be9;
-SDRAM[0].EmcBurstRefreshNum = 0x00000000;
-SDRAM[0].EmcPreRefreshReqCnt = 0x000006fa;
-SDRAM[0].EmcPdEx2Wr = 0x00000004;
-SDRAM[0].EmcPdEx2Rd = 0x00000015;
-SDRAM[0].EmcPChg2Pden = 0x00000001;
-SDRAM[0].EmcAct2Pden = 0x00000000;
-SDRAM[0].EmcAr2Pden = 0x000000e6;
-SDRAM[0].EmcRw2Pden = 0x0000001b;
-SDRAM[0].EmcTxsr = 0x000000fa;
-SDRAM[0].EmcTxsrDll = 0x00000200;
-SDRAM[0].EmcTcke = 0x00000006;
-SDRAM[0].EmcTckesr = 0x00000007;
-SDRAM[0].EmcTpd = 0x00000006;
-SDRAM[0].EmcTfaw = 0x00000022;
-SDRAM[0].EmcTrpab = 0x00000000;
-SDRAM[0].EmcTClkStable = 0x0000000a;
-SDRAM[0].EmcTClkStop = 0x0000000a;
-SDRAM[0].EmcTRefBw = 0x00001c29;
-SDRAM[0].EmcFbioCfg5 = 0x104ab898;
-SDRAM[0].EmcFbioCfg6 = 0x00000002;
-SDRAM[0].EmcFbioSpare = 0x00000000;
-SDRAM[0].EmcCfgRsv = 0xff00ff00;
-SDRAM[0].EmcMrs = 0x80000f15;
-SDRAM[0].EmcEmrs = 0x80100002;
-SDRAM[0].EmcEmrs2 = 0x80200020;
-SDRAM[0].EmcEmrs3 = 0x80300000;
-SDRAM[0].EmcMrw1 = 0x00000000;
-SDRAM[0].EmcMrw2 = 0x00000000;
-SDRAM[0].EmcMrw3 = 0x00000000;
-SDRAM[0].EmcMrw4 = 0x00000000;
-SDRAM[0].EmcMrwExtra = 0x00000000;
-SDRAM[0].EmcWarmBootMrwExtra = 0x00000000;
-SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000;
-SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000;
-SDRAM[0].EmcMrwResetCommand = 0x00000000;
-SDRAM[0].EmcMrwResetNInitWait = 0x00000000;
-SDRAM[0].EmcMrsWaitCnt = 0x00ce000e;
-SDRAM[0].EmcMrsWaitCnt2 = 0x00ce000e;
-SDRAM[0].EmcCfg = 0x73300000;
-SDRAM[0].EmcCfg2 = 0x000008a5;
-SDRAM[0].EmcCfgPipe = 0x00000000;
-SDRAM[0].EmcDbg = 0x01000c00;
-SDRAM[0].EmcCmdQ = 0x10004408;
-SDRAM[0].EmcMc2EmcQ = 0x06000404;
-SDRAM[0].EmcDynSelfRefControl = 0x800037ed;
-SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001;
-SDRAM[0].EmcCfgDigDll = 0xe00401b1;
-SDRAM[0].EmcCfgDigDllPeriod = 0x00008000;
-SDRAM[0].EmcDevSelect = 0x00000002;
-SDRAM[0].EmcSelDpdCtrl = 0x00040000;
-SDRAM[0].EmcDllXformDqs0 = 0x00000005;
-SDRAM[0].EmcDllXformDqs1 = 0x00000005;
-SDRAM[0].EmcDllXformDqs2 = 0x00000005;
-SDRAM[0].EmcDllXformDqs3 = 0x00000005;
-SDRAM[0].EmcDllXformDqs4 = 0x00000005;
-SDRAM[0].EmcDllXformDqs5 = 0x00000005;
-SDRAM[0].EmcDllXformDqs6 = 0x00000005;
-SDRAM[0].EmcDllXformDqs7 = 0x00000005;
-SDRAM[0].EmcDllXformDqs8 = 0x00000005;
-SDRAM[0].EmcDllXformDqs9 = 0x00000005;
-SDRAM[0].EmcDllXformDqs10 = 0x00000005;
-SDRAM[0].EmcDllXformDqs11 = 0x00000005;
-SDRAM[0].EmcDllXformDqs12 = 0x00000005;
-SDRAM[0].EmcDllXformDqs13 = 0x00000005;
-SDRAM[0].EmcDllXformDqs14 = 0x00000005;
-SDRAM[0].EmcDllXformDqs15 = 0x00000005;
-SDRAM[0].EmcDllXformQUse0 = 0x00000000;
-SDRAM[0].EmcDllXformQUse1 = 0x00000000;
-SDRAM[0].EmcDllXformQUse2 = 0x00000000;
-SDRAM[0].EmcDllXformQUse3 = 0x00000000;
-SDRAM[0].EmcDllXformQUse4 = 0x00000000;
-SDRAM[0].EmcDllXformQUse5 = 0x00000000;
-SDRAM[0].EmcDllXformQUse6 = 0x00000000;
-SDRAM[0].EmcDllXformQUse7 = 0x00000000;
-SDRAM[0].EmcDllXformAddr0 = 0x0000400e;
-SDRAM[0].EmcDllXformAddr1 = 0x0000400e;
-SDRAM[0].EmcDllXformAddr2 = 0x00000000;
-SDRAM[0].EmcDllXformAddr3 = 0x0000400e;
-SDRAM[0].EmcDllXformAddr4 = 0x0000400e;
-SDRAM[0].EmcDllXformAddr5 = 0x00000000;
-SDRAM[0].EmcDllXformQUse8 = 0x00000000;
-SDRAM[0].EmcDllXformQUse9 = 0x00000000;
-SDRAM[0].EmcDllXformQUse10 = 0x00000000;
-SDRAM[0].EmcDllXformQUse11 = 0x00000000;
-SDRAM[0].EmcDllXformQUse12 = 0x00000000;
-SDRAM[0].EmcDllXformQUse13 = 0x00000000;
-SDRAM[0].EmcDllXformQUse14 = 0x00000000;
-SDRAM[0].EmcDllXformQUse15 = 0x00000000;
-SDRAM[0].EmcDliTrimTxDqs0 = 0x00000000;
-SDRAM[0].EmcDliTrimTxDqs1 = 0x00000000;
-SDRAM[0].EmcDliTrimTxDqs2 = 0x00000000;
-SDRAM[0].EmcDliTrimTxDqs3 = 0x00000000;
-SDRAM[0].EmcDliTrimTxDqs4 = 0x00000000;
-SDRAM[0].EmcDliTrimTxDqs5 = 0x00000000;
-SDRAM[0].EmcDliTrimTxDqs6 = 0x00000000;
-SDRAM[0].EmcDliTrimTxDqs7 = 0x00000000;
-SDRAM[0].EmcDliTrimTxDqs8 = 0x00000000;
-SDRAM[0].EmcDliTrimTxDqs9 = 0x00000000;
-SDRAM[0].EmcDliTrimTxDqs10 = 0x00000000;
-SDRAM[0].EmcDliTrimTxDqs11 = 0x00000000;
-SDRAM[0].EmcDliTrimTxDqs12 = 0x00000000;
-SDRAM[0].EmcDliTrimTxDqs13 = 0x00000000;
-SDRAM[0].EmcDliTrimTxDqs14 = 0x00000000;
-SDRAM[0].EmcDliTrimTxDqs15 = 0x00000000;
-SDRAM[0].EmcDllXformDq0 = 0x00000006;
-SDRAM[0].EmcDllXformDq1 = 0x00000006;
-SDRAM[0].EmcDllXformDq2 = 0x00000006;
-SDRAM[0].EmcDllXformDq3 = 0x00000006;
-SDRAM[0].EmcDllXformDq4 = 0x00000006;
-SDRAM[0].EmcDllXformDq5 = 0x00000006;
-SDRAM[0].EmcDllXformDq6 = 0x00000006;
-SDRAM[0].EmcDllXformDq7 = 0x00000006;
-SDRAM[0].WarmBootWait = 0x00000002;
-SDRAM[0].EmcCttTermCtrl = 0x00000802;
-SDRAM[0].EmcOdtWrite = 0x00000000;
-SDRAM[0].EmcOdtRead = 0x00000000;
-SDRAM[0].EmcZcalInterval = 0x00020000;
-SDRAM[0].EmcZcalWaitCnt = 0x0000004c;
-SDRAM[0].EmcZcalMrwCmd = 0x80000000;
-SDRAM[0].EmcMrsResetDll = 0x00000000;
-SDRAM[0].EmcZcalInitDev0 = 0x80000011;
-SDRAM[0].EmcZcalInitDev1 = 0x00000000;
-SDRAM[0].EmcZcalInitWait = 0x00000001;
-SDRAM[0].EmcZcalWarmColdBootEnables = 0x00000003;
-SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab;
-SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000000;
-SDRAM[0].EmcZcalWarmBootWait = 0x00000001;
-SDRAM[0].EmcMrsWarmBootEnable = 0x00000001;
-SDRAM[0].EmcMrsResetDllWait = 0x00000000;
-SDRAM[0].EmcMrsExtra = 0x80000f15;
-SDRAM[0].EmcWarmBootMrsExtra = 0x80100002;
-SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000;
-SDRAM[0].EmcMrsDdr2DllReset = 0x00000000;
-SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000;
-SDRAM[0].EmcDdr2Wait = 0x00000000;
-SDRAM[0].EmcClkenOverride = 0x00000000;
-SDRAM[0].McDisExtraSnapLevels = 0x00000000;
-SDRAM[0].EmcExtraRefreshNum = 0x00000002;
-SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000;
-SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000;
-SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003;
-SDRAM[0].PmcVddpSel = 0x00000002;
-SDRAM[0].PmcVddpSelWait = 0x00000002;
-SDRAM[0].PmcDdrPwr = 0x00000003;
-SDRAM[0].PmcDdrCfg = 0x00002002;
-SDRAM[0].PmcIoDpd3Req = 0x4fff2f97;
-SDRAM[0].PmcIoDpd3ReqWait = 0x00000000;
-SDRAM[0].PmcRegShort = 0x00000000;
-SDRAM[0].PmcNoIoPower = 0x00000000;
-SDRAM[0].PmcPorDpdCtrlWait = 0x00000000;
-SDRAM[0].EmcXm2CmdPadCtrl = 0x100002a0;
-SDRAM[0].EmcXm2CmdPadCtrl2 = 0x770c0000;
-SDRAM[0].EmcXm2CmdPadCtrl3 = 0x050c0000;
-SDRAM[0].EmcXm2CmdPadCtrl4 = 0x00000000;
-SDRAM[0].EmcXm2CmdPadCtrl5 = 0x00111111;
-SDRAM[0].EmcXm2DqsPadCtrl = 0x770c1414;
-SDRAM[0].EmcXm2DqsPadCtrl2 = 0x0020013d;
-SDRAM[0].EmcXm2DqsPadCtrl3 = 0x55555520;
-SDRAM[0].EmcXm2DqsPadCtrl4 = 0x003cf3cf;
-SDRAM[0].EmcXm2DqsPadCtrl5 = 0x003cf3cf;
-SDRAM[0].EmcXm2DqsPadCtrl6 = 0x55555500;
-SDRAM[0].EmcXm2DqPadCtrl = 0x770c2990;
-SDRAM[0].EmcXm2DqPadCtrl2 = 0x00000000;
-SDRAM[0].EmcXm2DqPadCtrl3 = 0x00000000;
-SDRAM[0].EmcXm2ClkPadCtrl = 0x77ffc085;
-SDRAM[0].EmcXm2ClkPadCtrl2 = 0x00000303;
-SDRAM[0].EmcXm2CompPadCtrl = 0x81f1f108;
-SDRAM[0].EmcXm2VttGenPadCtrl = 0x07070004;
-SDRAM[0].EmcXm2VttGenPadCtrl2 = 0x00000000;
-SDRAM[0].EmcXm2VttGenPadCtrl3 = 0x016eeeee;
-SDRAM[0].EmcAcpdControl = 0x00000000;
-SDRAM[0].EmcSwizzleRank0ByteCfg = 0x00003120;
-SDRAM[0].EmcSwizzleRank0Byte0 = 0x25143067;
-SDRAM[0].EmcSwizzleRank0Byte1 = 0x45367102;
-SDRAM[0].EmcSwizzleRank0Byte2 = 0x47106253;
-SDRAM[0].EmcSwizzleRank0Byte3 = 0x04362175;
-SDRAM[0].EmcSwizzleRank1ByteCfg = 0x00003120;
-SDRAM[0].EmcSwizzleRank1Byte0 = 0x71546032;
-SDRAM[0].EmcSwizzleRank1Byte1 = 0x35104276;
-SDRAM[0].EmcSwizzleRank1Byte2 = 0x27043615;
-SDRAM[0].EmcSwizzleRank1Byte3 = 0x72306145;
-SDRAM[0].EmcDsrVttgenDrv = 0x0606003f;
-SDRAM[0].EmcTxdsrvttgen = 0x00000000;
-SDRAM[0].EmcBgbiasCtl0 = 0x00000000;
-SDRAM[0].McEmemAdrCfg = 0x00000000;
-SDRAM[0].McEmemAdrCfgDev0 = 0x00080303;
-SDRAM[0].McEmemAdrCfgDev1 = 0x00080303;
-SDRAM[0].McEmemAdrCfgBankMask0 = 0x00001248;
-SDRAM[0].McEmemAdrCfgBankMask1 = 0x00002490;
-SDRAM[0].McEmemAdrCfgBankMask2 = 0x00000920;
-SDRAM[0].McEmemAdrCfgBankSwizzle3 = 0x00000001;
-SDRAM[0].McEmemCfg = 0x00000800;
-SDRAM[0].McEmemArbCfg = 0x0e00000d;
-SDRAM[0].McEmemArbOutstandingReq = 0x80000040;
-SDRAM[0].McEmemArbTimingRcd = 0x00000005;
-SDRAM[0].McEmemArbTimingRp = 0x00000006;
-SDRAM[0].McEmemArbTimingRc = 0x00000016;
-SDRAM[0].McEmemArbTimingRas = 0x0000000e;
-SDRAM[0].McEmemArbTimingFaw = 0x00000011;
-SDRAM[0].McEmemArbTimingRrd = 0x00000002;
-SDRAM[0].McEmemArbTimingRap2Pre = 0x00000004;
-SDRAM[0].McEmemArbTimingWap2Pre = 0x0000000e;
-SDRAM[0].McEmemArbTimingR2R = 0x00000002;
-SDRAM[0].McEmemArbTimingW2W = 0x00000002;
-SDRAM[0].McEmemArbTimingR2W = 0x00000006;
-SDRAM[0].McEmemArbTimingW2R = 0x00000009;
-SDRAM[0].McEmemArbDaTurns = 0x09060202;
-SDRAM[0].McEmemArbDaCovers = 0x001a1016;
-SDRAM[0].McEmemArbMisc0 = 0x734e2a17;
-SDRAM[0].McEmemArbMisc1 = 0x70000f02;
-SDRAM[0].McEmemArbRing1Throttle = 0x001f0000;
-SDRAM[0].McEmemArbOverride = 0x10000000;
-SDRAM[0].McEmemArbOverride1 = 0x00000000;
-SDRAM[0].McEmemArbRsv = 0xff00ff00;
-SDRAM[0].McClkenOverride = 0x00000000;
-SDRAM[0].McStatControl = 0x00000000;
-SDRAM[0].McDisplaySnapRing = 0x00000003;
-SDRAM[0].McVideoProtectBom = 0xfff00000;
-SDRAM[0].McVideoProtectBomAdrHi = 0x00000000;
-SDRAM[0].McVideoProtectSizeMb = 0x00000000;
-SDRAM[0].McVideoProtectVprOverride = 0xe4bac743;
-SDRAM[0].McVideoProtectVprOverride1 = 0x00000013;
-SDRAM[0].McVideoProtectGpuOverride0 = 0x00000000;
-SDRAM[0].McVideoProtectGpuOverride1 = 0x00000000;
-SDRAM[0].McSecCarveoutBom = 0xfff00000;
-SDRAM[0].McSecCarveoutAdrHi = 0x00000000;
-SDRAM[0].McSecCarveoutSizeMb = 0x00000000;
-SDRAM[0].McVideoProtectWriteAccess = 0x00000000;
-SDRAM[0].McSecCarveoutProtectWriteAccess = 0x00000000;
-SDRAM[0].EmcCaTrainingEnable = 0x00000000;
-SDRAM[0].EmcCaTrainingTimingCntl1 = 0x1f7df7df;
-SDRAM[0].EmcCaTrainingTimingCntl2 = 0x0000001f;
-SDRAM[0].SwizzleRankByteEncode = 0x0000006f;
-SDRAM[0].BootRomPatchControl = 0x00000000;
-SDRAM[0].BootRomPatchData = 0x00000000;
-SDRAM[0].McMtsCarveoutBom = 0xfff00000;
-SDRAM[0].McMtsCarveoutAdrHi = 0x00000000;
-SDRAM[0].McMtsCarveoutSizeMb = 0x00000000;
-SDRAM[0].McMtsCarveoutRegCtrl = 0x00000000;
-#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x00000017;
-#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x000001bb;
-#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x006e0038;
-#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x006e0038;
-#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x006e003c;
-#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x006e0090;
-#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x006e0041;
-#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x006e0090;
-#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x006e0041;
-#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049;
-#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x006e0080;
-#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x006e0004;
-#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x006e0004;
-#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080016;
-#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x0000006e;
-#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x006e0004;
-#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x006e0019;
-#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x006e0018;
-#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x006e0024;
-#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x006e001b;
-#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x0000006e;
-#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036;
-#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x006e006e;
-#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036;
-#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x006e006e;
-#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff;
-#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029;
-#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x006e006e;
-#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x006e006e;
-#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x006e0065;
-#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x006e001c;
diff --git a/src/mainboard/google/nyan/bct/sdram-hynix-2GB-792.inc b/src/mainboard/google/nyan/bct/sdram-hynix-2GB-792.inc
new file mode 100644
index 0000000000..d175e7b4e4
--- /dev/null
+++ b/src/mainboard/google/nyan/bct/sdram-hynix-2GB-792.inc
@@ -0,0 +1,311 @@
+{ /* generated from sdram-0001-792-2GB.cfg; do not edit. */
+ .MemoryType = NvBootMemoryType_Ddr3,
+ .PllMInputDivider = 0x00000001,
+ .PllMFeedbackDivider = 0x00000042,
+ .PllMStableTime = 0x0000012c,
+ .PllMSetupControl = 0x00000000,
+ .PllMSelectDiv2 = 0x00000000,
+ .PllMPDLshiftPh45 = 0x00000001,
+ .PllMPDLshiftPh90 = 0x00000001,
+ .PllMPDLshiftPh135 = 0x00000001,
+ .PllMKCP = 0x00000000,
+ .PllMKVCO = 0x00000000,
+ .EmcBctSpare0 = 0x00000000,
+ .EmcBctSpare1 = 0x00000000,
+ .EmcBctSpare2 = 0x00000000,
+ .EmcBctSpare3 = 0x00000000,
+ .EmcBctSpare4 = 0x00000000,
+ .EmcBctSpare5 = 0x00000000,
+ .EmcBctSpare6 = 0x00000000,
+ .EmcBctSpare7 = 0x00000000,
+ .EmcBctSpare8 = 0x00000000,
+ .EmcBctSpare9 = 0x00000000,
+ .EmcBctSpare10 = 0x00000000,
+ .EmcBctSpare11 = 0x00000000,
+ .EmcClockSource = 0x80000000,
+ .EmcAutoCalInterval = 0x001fffff,
+ .EmcAutoCalConfig = 0xa1430000,
+ .EmcAutoCalConfig2 = 0x00000000,
+ .EmcAutoCalConfig3 = 0x00000000,
+ .EmcAutoCalWait = 0x00000190,
+ .EmcAdrCfg = 0x00000000,
+ .EmcPinProgramWait = 0x00000001,
+ .EmcPinExtraWait = 0x00000000,
+ .EmcTimingControlWait = 0x00000000,
+ .EmcRc = 0x00000025,
+ .EmcRfc = 0x000000cd,
+ .EmcRfcSlr = 0x00000000,
+ .EmcRas = 0x00000019,
+ .EmcRp = 0x0000000a,
+ .EmcR2r = 0x00000000,
+ .EmcW2w = 0x00000000,
+ .EmcR2w = 0x00000007,
+ .EmcW2r = 0x0000000d,
+ .EmcR2p = 0x00000004,
+ .EmcW2p = 0x00000013,
+ .EmcRdRcd = 0x0000000a,
+ .EmcWrRcd = 0x0000000a,
+ .EmcRrd = 0x00000003,
+ .EmcRext = 0x00000002,
+ .EmcWext = 0x00000000,
+ .EmcWdv = 0x00000006,
+ .EmcWdvMask = 0x00000006,
+ .EmcQUse = 0x0000000b,
+ .EmcQuseWidth = 0x00000002,
+ .EmcIbdly = 0x00000000,
+ .EmcEInput = 0x00000003,
+ .EmcEInputDuration = 0x0000000c,
+ .EmcPutermExtra = 0x00090000,
+ .EmcPutermWidth = 0x00000004,
+ .EmcPutermAdj = 0x00000000,
+ .EmcCdbCntl1 = 0x00000000,
+ .EmcCdbCntl2 = 0x00000000,
+ .EmcCdbCntl3 = 0x00000000,
+ .EmcQRst = 0x00000002,
+ .EmcQSafe = 0x00000011,
+ .EmcRdv = 0x00000017,
+ .EmcRdvMask = 0x00000019,
+ .EmcQpop = 0x0000000f,
+ .EmcCtt = 0x00000000,
+ .EmcCttDuration = 0x00000004,
+ .EmcRefresh = 0x000017eb,
+ .EmcBurstRefreshNum = 0x00000000,
+ .EmcPreRefreshReqCnt = 0x000005fa,
+ .EmcPdEx2Wr = 0x00000003,
+ .EmcPdEx2Rd = 0x00000003,
+ .EmcPChg2Pden = 0x00000001,
+ .EmcAct2Pden = 0x00000000,
+ .EmcAr2Pden = 0x000000c7,
+ .EmcRw2Pden = 0x00000018,
+ .EmcTxsr = 0x000000d7,
+ .EmcTxsrDll = 0x00000200,
+ .EmcTcke = 0x00000005,
+ .EmcTckesr = 0x00000006,
+ .EmcTpd = 0x00000005,
+ .EmcTfaw = 0x0000001d,
+ .EmcTrpab = 0x00000000,
+ .EmcTClkStable = 0x00000008,
+ .EmcTClkStop = 0x00000008,
+ .EmcTRefBw = 0x0000182c,
+ .EmcFbioCfg5 = 0x104ab898,
+ .EmcFbioCfg6 = 0x00000002,
+ .EmcFbioSpare = 0x00000000,
+ .EmcCfgRsv = 0xff00ff00,
+ .EmcMrs = 0x80001d71,
+ .EmcEmrs = 0x80100002,
+ .EmcEmrs2 = 0x80200018,
+ .EmcEmrs3 = 0x80300000,
+ .EmcMrw1 = 0x00000000,
+ .EmcMrw2 = 0x00000000,
+ .EmcMrw3 = 0x00000000,
+ .EmcMrw4 = 0x00000000,
+ .EmcMrwExtra = 0x00000000,
+ .EmcWarmBootMrwExtra = 0x00000000,
+ .EmcWarmBootExtraModeRegWriteEnable = 0x00000000,
+ .EmcExtraModeRegWriteEnable = 0x00000000,
+ .EmcMrwResetCommand = 0x00000000,
+ .EmcMrwResetNInitWait = 0x00000000,
+ .EmcMrsWaitCnt = 0x00f7000e,
+ .EmcMrsWaitCnt2 = 0x00f7000e,
+ .EmcCfg = 0x73300000,
+ .EmcCfg2 = 0x0000089d,
+ .EmcCfgPipe = 0x000040a0,
+ .EmcDbg = 0x01000c00,
+ .EmcCmdQ = 0x10004408,
+ .EmcMc2EmcQ = 0x06000404,
+ .EmcDynSelfRefControl = 0x80003025,
+ .AhbArbitrationXbarCtrlMemInitDone = 0x00000001,
+ .EmcCfgDigDll = 0xe00701b1,
+ .EmcCfgDigDllPeriod = 0x00008000,
+ .EmcDevSelect = 0x00000002,
+ .EmcSelDpdCtrl = 0x00040000,
+ .EmcDllXformDqs0 = 0x00000008,
+ .EmcDllXformDqs1 = 0x00000008,
+ .EmcDllXformDqs2 = 0x00000008,
+ .EmcDllXformDqs3 = 0x00000008,
+ .EmcDllXformDqs4 = 0x00000008,
+ .EmcDllXformDqs5 = 0x00000008,
+ .EmcDllXformDqs6 = 0x00000008,
+ .EmcDllXformDqs7 = 0x00000008,
+ .EmcDllXformDqs8 = 0x00000008,
+ .EmcDllXformDqs9 = 0x00000008,
+ .EmcDllXformDqs10 = 0x00000008,
+ .EmcDllXformDqs11 = 0x00000008,
+ .EmcDllXformDqs12 = 0x00000008,
+ .EmcDllXformDqs13 = 0x00000008,
+ .EmcDllXformDqs14 = 0x00000008,
+ .EmcDllXformDqs15 = 0x00000008,
+ .EmcDllXformQUse0 = 0x00000000,
+ .EmcDllXformQUse1 = 0x00000000,
+ .EmcDllXformQUse2 = 0x00000000,
+ .EmcDllXformQUse3 = 0x00000000,
+ .EmcDllXformQUse4 = 0x00000000,
+ .EmcDllXformQUse5 = 0x00000000,
+ .EmcDllXformQUse6 = 0x00000000,
+ .EmcDllXformQUse7 = 0x00000000,
+ .EmcDllXformAddr0 = 0x0000000e,
+ .EmcDllXformAddr1 = 0x0000000e,
+ .EmcDllXformAddr2 = 0x00000000,
+ .EmcDllXformAddr3 = 0x0000000e,
+ .EmcDllXformAddr4 = 0x00000000,
+ .EmcDllXformAddr5 = 0x00000000,
+ .EmcDllXformQUse8 = 0x00000000,
+ .EmcDllXformQUse9 = 0x00000000,
+ .EmcDllXformQUse10 = 0x00000000,
+ .EmcDllXformQUse11 = 0x00000000,
+ .EmcDllXformQUse12 = 0x00000000,
+ .EmcDllXformQUse13 = 0x00000000,
+ .EmcDllXformQUse14 = 0x00000000,
+ .EmcDllXformQUse15 = 0x00000000,
+ .EmcDliTrimTxDqs0 = 0x00000000,
+ .EmcDliTrimTxDqs1 = 0x00000000,
+ .EmcDliTrimTxDqs2 = 0x00000000,
+ .EmcDliTrimTxDqs3 = 0x00000000,
+ .EmcDliTrimTxDqs4 = 0x00000000,
+ .EmcDliTrimTxDqs5 = 0x00000000,
+ .EmcDliTrimTxDqs6 = 0x00000000,
+ .EmcDliTrimTxDqs7 = 0x00000000,
+ .EmcDliTrimTxDqs8 = 0x00000000,
+ .EmcDliTrimTxDqs9 = 0x00000000,
+ .EmcDliTrimTxDqs10 = 0x00000000,
+ .EmcDliTrimTxDqs11 = 0x00000000,
+ .EmcDliTrimTxDqs12 = 0x00000000,
+ .EmcDliTrimTxDqs13 = 0x00000000,
+ .EmcDliTrimTxDqs14 = 0x00000000,
+ .EmcDliTrimTxDqs15 = 0x00000000,
+ .EmcDllXformDq0 = 0x0000000b,
+ .EmcDllXformDq1 = 0x0000000b,
+ .EmcDllXformDq2 = 0x0000000b,
+ .EmcDllXformDq3 = 0x0000000b,
+ .EmcDllXformDq4 = 0x0000000b,
+ .EmcDllXformDq5 = 0x0000000b,
+ .EmcDllXformDq6 = 0x0000000b,
+ .EmcDllXformDq7 = 0x0000000b,
+ .WarmBootWait = 0x00000002,
+ .EmcCttTermCtrl = 0x00000802,
+ .EmcOdtWrite = 0x00000000,
+ .EmcOdtRead = 0x00000000,
+ .EmcZcalInterval = 0x00020000,
+ .EmcZcalWaitCnt = 0x00000042,
+ .EmcZcalMrwCmd = 0x80000000,
+ .EmcMrsResetDll = 0x00000000,
+ .EmcZcalInitDev0 = 0x80000011,
+ .EmcZcalInitDev1 = 0x00000000,
+ .EmcZcalInitWait = 0x00000001,
+ .EmcZcalWarmColdBootEnables = 0x00000003,
+ .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab,
+ .EmcZqCalDdr3WarmBoot = 0x00000000,
+ .EmcZcalWarmBootWait = 0x00000001,
+ .EmcMrsWarmBootEnable = 0x00000001,
+ .EmcMrsResetDllWait = 0x00000000,
+ .EmcMrsExtra = 0x80001d71,
+ .EmcWarmBootMrsExtra = 0x80100002,
+ .EmcEmrsDdr2DllEnable = 0x00000000,
+ .EmcMrsDdr2DllReset = 0x00000000,
+ .EmcEmrsDdr2OcdCalib = 0x00000000,
+ .EmcDdr2Wait = 0x00000000,
+ .EmcClkenOverride = 0x00000000,
+ .McDisExtraSnapLevels = 0x00000000,
+ .EmcExtraRefreshNum = 0x00000002,
+ .EmcClkenOverrideAllWarmBoot = 0x00000000,
+ .McClkenOverrideAllWarmBoot = 0x00000000,
+ .EmcCfgDigDllPeriodWarmBoot = 0x00000003,
+ .PmcVddpSel = 0x00000002,
+ .PmcVddpSelWait = 0x00000002,
+ .PmcDdrPwr = 0x00000003,
+ .PmcDdrCfg = 0x00002002,
+ .PmcIoDpd3Req = 0x4fff2f97,
+ .PmcIoDpd3ReqWait = 0x00000000,
+ .PmcRegShort = 0x00000000,
+ .PmcNoIoPower = 0x00000000,
+ .PmcPorDpdCtrlWait = 0x00000000,
+ .EmcXm2CmdPadCtrl = 0x100002a0,
+ .EmcXm2CmdPadCtrl2 = 0x770c0000,
+ .EmcXm2CmdPadCtrl3 = 0x050c0000,
+ .EmcXm2CmdPadCtrl4 = 0x00000000,
+ .EmcXm2CmdPadCtrl5 = 0x00111111,
+ .EmcXm2DqsPadCtrl = 0x770c1414,
+ .EmcXm2DqsPadCtrl2 = 0x0020013d,
+ .EmcXm2DqsPadCtrl3 = 0x61861820,
+ .EmcXm2DqsPadCtrl4 = 0x00514514,
+ .EmcXm2DqsPadCtrl5 = 0x00514514,
+ .EmcXm2DqsPadCtrl6 = 0x61861800,
+ .EmcXm2DqPadCtrl = 0x770c2990,
+ .EmcXm2DqPadCtrl2 = 0x00000000,
+ .EmcXm2DqPadCtrl3 = 0x00000000,
+ .EmcXm2ClkPadCtrl = 0x77ffc085,
+ .EmcXm2ClkPadCtrl2 = 0x00000707,
+ .EmcXm2CompPadCtrl = 0x81f1f108,
+ .EmcXm2VttGenPadCtrl = 0x07070004,
+ .EmcXm2VttGenPadCtrl2 = 0x00000000,
+ .EmcXm2VttGenPadCtrl3 = 0x017fffff,
+ .EmcAcpdControl = 0x00000000,
+ .EmcSwizzleRank0ByteCfg = 0x00003120,
+ .EmcSwizzleRank0Byte0 = 0x25143067,
+ .EmcSwizzleRank0Byte1 = 0x45367102,
+ .EmcSwizzleRank0Byte2 = 0x47106253,
+ .EmcSwizzleRank0Byte3 = 0x04362175,
+ .EmcSwizzleRank1ByteCfg = 0x00003120,
+ .EmcSwizzleRank1Byte0 = 0x71546032,
+ .EmcSwizzleRank1Byte1 = 0x35104276,
+ .EmcSwizzleRank1Byte2 = 0x27043615,
+ .EmcSwizzleRank1Byte3 = 0x72306145,
+ .EmcDsrVttgenDrv = 0x0505003f,
+ .EmcTxdsrvttgen = 0x00000000,
+ .EmcBgbiasCtl0 = 0x00000000,
+ .McEmemAdrCfg = 0x00000000,
+ .McEmemAdrCfgDev0 = 0x00080303,
+ .McEmemAdrCfgDev1 = 0x00080303,
+ .McEmemAdrCfgBankMask0 = 0x00001248,
+ .McEmemAdrCfgBankMask1 = 0x00002490,
+ .McEmemAdrCfgBankMask2 = 0x00000920,
+ .McEmemAdrCfgBankSwizzle3 = 0x00000001,
+ .McEmemCfg = 0x00000800,
+ .McEmemArbCfg = 0x0e00000b,
+ .McEmemArbOutstandingReq = 0x80000040,
+ .McEmemArbTimingRcd = 0x00000004,
+ .McEmemArbTimingRp = 0x00000005,
+ .McEmemArbTimingRc = 0x00000013,
+ .McEmemArbTimingRas = 0x0000000c,
+ .McEmemArbTimingFaw = 0x0000000f,
+ .McEmemArbTimingRrd = 0x00000002,
+ .McEmemArbTimingRap2Pre = 0x00000003,
+ .McEmemArbTimingWap2Pre = 0x0000000c,
+ .McEmemArbTimingR2R = 0x00000002,
+ .McEmemArbTimingW2W = 0x00000002,
+ .McEmemArbTimingR2W = 0x00000005,
+ .McEmemArbTimingW2R = 0x00000008,
+ .McEmemArbDaTurns = 0x08050202,
+ .McEmemArbDaCovers = 0x00170e13,
+ .McEmemArbMisc0 = 0x736c2414,
+ .McEmemArbMisc1 = 0x70000f02,
+ .McEmemArbRing1Throttle = 0x001f0000,
+ .McEmemArbOverride = 0x10000000,
+ .McEmemArbOverride1 = 0x00000000,
+ .McEmemArbRsv = 0xff00ff00,
+ .McClkenOverride = 0x00000000,
+ .McStatControl = 0x00000000,
+ .McDisplaySnapRing = 0x00000003,
+ .McVideoProtectBom = 0xfff00000,
+ .McVideoProtectBomAdrHi = 0x00000000,
+ .McVideoProtectSizeMb = 0x00000000,
+ .McVideoProtectVprOverride = 0xe4bac743,
+ .McVideoProtectVprOverride1 = 0x00000013,
+ .McVideoProtectGpuOverride0 = 0x00000000,
+ .McVideoProtectGpuOverride1 = 0x00000000,
+ .McSecCarveoutBom = 0xfff00000,
+ .McSecCarveoutAdrHi = 0x00000000,
+ .McSecCarveoutSizeMb = 0x00000000,
+ .McVideoProtectWriteAccess = 0x00000000,
+ .McSecCarveoutProtectWriteAccess = 0x00000000,
+ .EmcCaTrainingEnable = 0x00000000,
+ .EmcCaTrainingTimingCntl1 = 0x1f7df7df,
+ .EmcCaTrainingTimingCntl2 = 0x0000001f,
+ .SwizzleRankByteEncode = 0x0000006f,
+ .BootRomPatchControl = 0x00000000,
+ .BootRomPatchData = 0x00000000,
+ .McMtsCarveoutBom = 0xfff00000,
+ .McMtsCarveoutAdrHi = 0x00000000,
+ .McMtsCarveoutSizeMb = 0x00000000,
+ .McMtsCarveoutRegCtrl = 0x00000000,
+},
diff --git a/src/mainboard/google/nyan/bct/sdram-hynix-2GB-924.inc b/src/mainboard/google/nyan/bct/sdram-hynix-2GB-924.inc
new file mode 100644
index 0000000000..e4d4faf24a
--- /dev/null
+++ b/src/mainboard/google/nyan/bct/sdram-hynix-2GB-924.inc
@@ -0,0 +1,311 @@
+{ /* generated from sdram-0001-924-2GB.cfg; do not edit. */
+ .MemoryType = NvBootMemoryType_Ddr3,
+ .PllMInputDivider = 0x00000001,
+ .PllMFeedbackDivider = 0x0000004d,
+ .PllMStableTime = 0x0000012c,
+ .PllMSetupControl = 0x00000000,
+ .PllMSelectDiv2 = 0x00000000,
+ .PllMPDLshiftPh45 = 0x00000001,
+ .PllMPDLshiftPh90 = 0x00000001,
+ .PllMPDLshiftPh135 = 0x00000001,
+ .PllMKCP = 0x00000000,
+ .PllMKVCO = 0x00000000,
+ .EmcBctSpare0 = 0x00000000,
+ .EmcBctSpare1 = 0x00000000,
+ .EmcBctSpare2 = 0x00000000,
+ .EmcBctSpare3 = 0x00000000,
+ .EmcBctSpare4 = 0x00000000,
+ .EmcBctSpare5 = 0x00000000,
+ .EmcBctSpare6 = 0x00000000,
+ .EmcBctSpare7 = 0x00000000,
+ .EmcBctSpare8 = 0x00000000,
+ .EmcBctSpare9 = 0x00000000,
+ .EmcBctSpare10 = 0x00000000,
+ .EmcBctSpare11 = 0x00000000,
+ .EmcClockSource = 0x80000000,
+ .EmcAutoCalInterval = 0x001fffff,
+ .EmcAutoCalConfig = 0xa1430404,
+ .EmcAutoCalConfig2 = 0x00000000,
+ .EmcAutoCalConfig3 = 0x00000000,
+ .EmcAutoCalWait = 0x00000190,
+ .EmcAdrCfg = 0x00000000,
+ .EmcPinProgramWait = 0x00000001,
+ .EmcPinExtraWait = 0x00000000,
+ .EmcTimingControlWait = 0x00000000,
+ .EmcRc = 0x0000002b,
+ .EmcRfc = 0x000000ef,
+ .EmcRfcSlr = 0x00000000,
+ .EmcRas = 0x0000001e,
+ .EmcRp = 0x0000000b,
+ .EmcR2r = 0x00000000,
+ .EmcW2w = 0x00000000,
+ .EmcR2w = 0x00000008,
+ .EmcW2r = 0x0000000f,
+ .EmcR2p = 0x00000005,
+ .EmcW2p = 0x00000016,
+ .EmcRdRcd = 0x0000000b,
+ .EmcWrRcd = 0x0000000b,
+ .EmcRrd = 0x00000004,
+ .EmcRext = 0x00000002,
+ .EmcWext = 0x00000000,
+ .EmcWdv = 0x00000006,
+ .EmcWdvMask = 0x00000006,
+ .EmcQUse = 0x0000000c,
+ .EmcQuseWidth = 0x00000002,
+ .EmcIbdly = 0x00000000,
+ .EmcEInput = 0x00000002,
+ .EmcEInputDuration = 0x0000000e,
+ .EmcPutermExtra = 0x000a0000,
+ .EmcPutermWidth = 0x00000004,
+ .EmcPutermAdj = 0x00000000,
+ .EmcCdbCntl1 = 0x00000000,
+ .EmcCdbCntl2 = 0x00000000,
+ .EmcCdbCntl3 = 0x00000000,
+ .EmcQRst = 0x00000001,
+ .EmcQSafe = 0x00000015,
+ .EmcRdv = 0x0000001b,
+ .EmcRdvMask = 0x0000001d,
+ .EmcQpop = 0x00000010,
+ .EmcCtt = 0x00000000,
+ .EmcCttDuration = 0x00000004,
+ .EmcRefresh = 0x00001be9,
+ .EmcBurstRefreshNum = 0x00000000,
+ .EmcPreRefreshReqCnt = 0x000006fa,
+ .EmcPdEx2Wr = 0x00000004,
+ .EmcPdEx2Rd = 0x00000015,
+ .EmcPChg2Pden = 0x00000001,
+ .EmcAct2Pden = 0x00000000,
+ .EmcAr2Pden = 0x000000e6,
+ .EmcRw2Pden = 0x0000001b,
+ .EmcTxsr = 0x000000fa,
+ .EmcTxsrDll = 0x00000200,
+ .EmcTcke = 0x00000006,
+ .EmcTckesr = 0x00000007,
+ .EmcTpd = 0x00000006,
+ .EmcTfaw = 0x00000022,
+ .EmcTrpab = 0x00000000,
+ .EmcTClkStable = 0x0000000a,
+ .EmcTClkStop = 0x0000000a,
+ .EmcTRefBw = 0x00001c29,
+ .EmcFbioCfg5 = 0x104ab898,
+ .EmcFbioCfg6 = 0x00000002,
+ .EmcFbioSpare = 0x00000000,
+ .EmcCfgRsv = 0xff00ff00,
+ .EmcMrs = 0x80000f15,
+ .EmcEmrs = 0x80100002,
+ .EmcEmrs2 = 0x80200020,
+ .EmcEmrs3 = 0x80300000,
+ .EmcMrw1 = 0x00000000,
+ .EmcMrw2 = 0x00000000,
+ .EmcMrw3 = 0x00000000,
+ .EmcMrw4 = 0x00000000,
+ .EmcMrwExtra = 0x00000000,
+ .EmcWarmBootMrwExtra = 0x00000000,
+ .EmcWarmBootExtraModeRegWriteEnable = 0x00000000,
+ .EmcExtraModeRegWriteEnable = 0x00000000,
+ .EmcMrwResetCommand = 0x00000000,
+ .EmcMrwResetNInitWait = 0x00000000,
+ .EmcMrsWaitCnt = 0x00ce000e,
+ .EmcMrsWaitCnt2 = 0x00ce000e,
+ .EmcCfg = 0x73300000,
+ .EmcCfg2 = 0x000008a5,
+ .EmcCfgPipe = 0x00000000,
+ .EmcDbg = 0x01000c00,
+ .EmcCmdQ = 0x10004408,
+ .EmcMc2EmcQ = 0x06000404,
+ .EmcDynSelfRefControl = 0x800037ed,
+ .AhbArbitrationXbarCtrlMemInitDone = 0x00000001,
+ .EmcCfgDigDll = 0xe00401b1,
+ .EmcCfgDigDllPeriod = 0x00008000,
+ .EmcDevSelect = 0x00000002,
+ .EmcSelDpdCtrl = 0x00040000,
+ .EmcDllXformDqs0 = 0x00000005,
+ .EmcDllXformDqs1 = 0x00000005,
+ .EmcDllXformDqs2 = 0x00000005,
+ .EmcDllXformDqs3 = 0x00000005,
+ .EmcDllXformDqs4 = 0x00000005,
+ .EmcDllXformDqs5 = 0x00000005,
+ .EmcDllXformDqs6 = 0x00000005,
+ .EmcDllXformDqs7 = 0x00000005,
+ .EmcDllXformDqs8 = 0x00000005,
+ .EmcDllXformDqs9 = 0x00000005,
+ .EmcDllXformDqs10 = 0x00000005,
+ .EmcDllXformDqs11 = 0x00000005,
+ .EmcDllXformDqs12 = 0x00000005,
+ .EmcDllXformDqs13 = 0x00000005,
+ .EmcDllXformDqs14 = 0x00000005,
+ .EmcDllXformDqs15 = 0x00000005,
+ .EmcDllXformQUse0 = 0x00000000,
+ .EmcDllXformQUse1 = 0x00000000,
+ .EmcDllXformQUse2 = 0x00000000,
+ .EmcDllXformQUse3 = 0x00000000,
+ .EmcDllXformQUse4 = 0x00000000,
+ .EmcDllXformQUse5 = 0x00000000,
+ .EmcDllXformQUse6 = 0x00000000,
+ .EmcDllXformQUse7 = 0x00000000,
+ .EmcDllXformAddr0 = 0x0000400e,
+ .EmcDllXformAddr1 = 0x0000400e,
+ .EmcDllXformAddr2 = 0x00000000,
+ .EmcDllXformAddr3 = 0x0000400e,
+ .EmcDllXformAddr4 = 0x0000400e,
+ .EmcDllXformAddr5 = 0x00000000,
+ .EmcDllXformQUse8 = 0x00000000,
+ .EmcDllXformQUse9 = 0x00000000,
+ .EmcDllXformQUse10 = 0x00000000,
+ .EmcDllXformQUse11 = 0x00000000,
+ .EmcDllXformQUse12 = 0x00000000,
+ .EmcDllXformQUse13 = 0x00000000,
+ .EmcDllXformQUse14 = 0x00000000,
+ .EmcDllXformQUse15 = 0x00000000,
+ .EmcDliTrimTxDqs0 = 0x00000000,
+ .EmcDliTrimTxDqs1 = 0x00000000,
+ .EmcDliTrimTxDqs2 = 0x00000000,
+ .EmcDliTrimTxDqs3 = 0x00000000,
+ .EmcDliTrimTxDqs4 = 0x00000000,
+ .EmcDliTrimTxDqs5 = 0x00000000,
+ .EmcDliTrimTxDqs6 = 0x00000000,
+ .EmcDliTrimTxDqs7 = 0x00000000,
+ .EmcDliTrimTxDqs8 = 0x00000000,
+ .EmcDliTrimTxDqs9 = 0x00000000,
+ .EmcDliTrimTxDqs10 = 0x00000000,
+ .EmcDliTrimTxDqs11 = 0x00000000,
+ .EmcDliTrimTxDqs12 = 0x00000000,
+ .EmcDliTrimTxDqs13 = 0x00000000,
+ .EmcDliTrimTxDqs14 = 0x00000000,
+ .EmcDliTrimTxDqs15 = 0x00000000,
+ .EmcDllXformDq0 = 0x00000006,
+ .EmcDllXformDq1 = 0x00000006,
+ .EmcDllXformDq2 = 0x00000006,
+ .EmcDllXformDq3 = 0x00000006,
+ .EmcDllXformDq4 = 0x00000006,
+ .EmcDllXformDq5 = 0x00000006,
+ .EmcDllXformDq6 = 0x00000006,
+ .EmcDllXformDq7 = 0x00000006,
+ .WarmBootWait = 0x00000002,
+ .EmcCttTermCtrl = 0x00000802,
+ .EmcOdtWrite = 0x00000000,
+ .EmcOdtRead = 0x00000000,
+ .EmcZcalInterval = 0x00020000,
+ .EmcZcalWaitCnt = 0x0000004c,
+ .EmcZcalMrwCmd = 0x80000000,
+ .EmcMrsResetDll = 0x00000000,
+ .EmcZcalInitDev0 = 0x80000011,
+ .EmcZcalInitDev1 = 0x00000000,
+ .EmcZcalInitWait = 0x00000001,
+ .EmcZcalWarmColdBootEnables = 0x00000003,
+ .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab,
+ .EmcZqCalDdr3WarmBoot = 0x00000000,
+ .EmcZcalWarmBootWait = 0x00000001,
+ .EmcMrsWarmBootEnable = 0x00000001,
+ .EmcMrsResetDllWait = 0x00000000,
+ .EmcMrsExtra = 0x80000f15,
+ .EmcWarmBootMrsExtra = 0x80100002,
+ .EmcEmrsDdr2DllEnable = 0x00000000,
+ .EmcMrsDdr2DllReset = 0x00000000,
+ .EmcEmrsDdr2OcdCalib = 0x00000000,
+ .EmcDdr2Wait = 0x00000000,
+ .EmcClkenOverride = 0x00000000,
+ .McDisExtraSnapLevels = 0x00000000,
+ .EmcExtraRefreshNum = 0x00000002,
+ .EmcClkenOverrideAllWarmBoot = 0x00000000,
+ .McClkenOverrideAllWarmBoot = 0x00000000,
+ .EmcCfgDigDllPeriodWarmBoot = 0x00000003,
+ .PmcVddpSel = 0x00000002,
+ .PmcVddpSelWait = 0x00000002,
+ .PmcDdrPwr = 0x00000003,
+ .PmcDdrCfg = 0x00002002,
+ .PmcIoDpd3Req = 0x4fff2f97,
+ .PmcIoDpd3ReqWait = 0x00000000,
+ .PmcRegShort = 0x00000000,
+ .PmcNoIoPower = 0x00000000,
+ .PmcPorDpdCtrlWait = 0x00000000,
+ .EmcXm2CmdPadCtrl = 0x100002a0,
+ .EmcXm2CmdPadCtrl2 = 0x770c0000,
+ .EmcXm2CmdPadCtrl3 = 0x050c0000,
+ .EmcXm2CmdPadCtrl4 = 0x00000000,
+ .EmcXm2CmdPadCtrl5 = 0x00111111,
+ .EmcXm2DqsPadCtrl = 0x770c1414,
+ .EmcXm2DqsPadCtrl2 = 0x0020013d,
+ .EmcXm2DqsPadCtrl3 = 0x55555520,
+ .EmcXm2DqsPadCtrl4 = 0x003cf3cf,
+ .EmcXm2DqsPadCtrl5 = 0x003cf3cf,
+ .EmcXm2DqsPadCtrl6 = 0x55555500,
+ .EmcXm2DqPadCtrl = 0x770c2990,
+ .EmcXm2DqPadCtrl2 = 0x00000000,
+ .EmcXm2DqPadCtrl3 = 0x00000000,
+ .EmcXm2ClkPadCtrl = 0x77ffc085,
+ .EmcXm2ClkPadCtrl2 = 0x00000303,
+ .EmcXm2CompPadCtrl = 0x81f1f108,
+ .EmcXm2VttGenPadCtrl = 0x07070004,
+ .EmcXm2VttGenPadCtrl2 = 0x00000000,
+ .EmcXm2VttGenPadCtrl3 = 0x016eeeee,
+ .EmcAcpdControl = 0x00000000,
+ .EmcSwizzleRank0ByteCfg = 0x00003120,
+ .EmcSwizzleRank0Byte0 = 0x25143067,
+ .EmcSwizzleRank0Byte1 = 0x45367102,
+ .EmcSwizzleRank0Byte2 = 0x47106253,
+ .EmcSwizzleRank0Byte3 = 0x04362175,
+ .EmcSwizzleRank1ByteCfg = 0x00003120,
+ .EmcSwizzleRank1Byte0 = 0x71546032,
+ .EmcSwizzleRank1Byte1 = 0x35104276,
+ .EmcSwizzleRank1Byte2 = 0x27043615,
+ .EmcSwizzleRank1Byte3 = 0x72306145,
+ .EmcDsrVttgenDrv = 0x0606003f,
+ .EmcTxdsrvttgen = 0x00000000,
+ .EmcBgbiasCtl0 = 0x00000000,
+ .McEmemAdrCfg = 0x00000000,
+ .McEmemAdrCfgDev0 = 0x00080303,
+ .McEmemAdrCfgDev1 = 0x00080303,
+ .McEmemAdrCfgBankMask0 = 0x00001248,
+ .McEmemAdrCfgBankMask1 = 0x00002490,
+ .McEmemAdrCfgBankMask2 = 0x00000920,
+ .McEmemAdrCfgBankSwizzle3 = 0x00000001,
+ .McEmemCfg = 0x00000800,
+ .McEmemArbCfg = 0x0e00000d,
+ .McEmemArbOutstandingReq = 0x80000040,
+ .McEmemArbTimingRcd = 0x00000005,
+ .McEmemArbTimingRp = 0x00000006,
+ .McEmemArbTimingRc = 0x00000016,
+ .McEmemArbTimingRas = 0x0000000e,
+ .McEmemArbTimingFaw = 0x00000011,
+ .McEmemArbTimingRrd = 0x00000002,
+ .McEmemArbTimingRap2Pre = 0x00000004,
+ .McEmemArbTimingWap2Pre = 0x0000000e,
+ .McEmemArbTimingR2R = 0x00000002,
+ .McEmemArbTimingW2W = 0x00000002,
+ .McEmemArbTimingR2W = 0x00000006,
+ .McEmemArbTimingW2R = 0x00000009,
+ .McEmemArbDaTurns = 0x09060202,
+ .McEmemArbDaCovers = 0x001a1016,
+ .McEmemArbMisc0 = 0x734e2a17,
+ .McEmemArbMisc1 = 0x70000f02,
+ .McEmemArbRing1Throttle = 0x001f0000,
+ .McEmemArbOverride = 0x10000000,
+ .McEmemArbOverride1 = 0x00000000,
+ .McEmemArbRsv = 0xff00ff00,
+ .McClkenOverride = 0x00000000,
+ .McStatControl = 0x00000000,
+ .McDisplaySnapRing = 0x00000003,
+ .McVideoProtectBom = 0xfff00000,
+ .McVideoProtectBomAdrHi = 0x00000000,
+ .McVideoProtectSizeMb = 0x00000000,
+ .McVideoProtectVprOverride = 0xe4bac743,
+ .McVideoProtectVprOverride1 = 0x00000013,
+ .McVideoProtectGpuOverride0 = 0x00000000,
+ .McVideoProtectGpuOverride1 = 0x00000000,
+ .McSecCarveoutBom = 0xfff00000,
+ .McSecCarveoutAdrHi = 0x00000000,
+ .McSecCarveoutSizeMb = 0x00000000,
+ .McVideoProtectWriteAccess = 0x00000000,
+ .McSecCarveoutProtectWriteAccess = 0x00000000,
+ .EmcCaTrainingEnable = 0x00000000,
+ .EmcCaTrainingTimingCntl1 = 0x1f7df7df,
+ .EmcCaTrainingTimingCntl2 = 0x0000001f,
+ .SwizzleRankByteEncode = 0x0000006f,
+ .BootRomPatchControl = 0x00000000,
+ .BootRomPatchData = 0x00000000,
+ .McMtsCarveoutBom = 0xfff00000,
+ .McMtsCarveoutAdrHi = 0x00000000,
+ .McMtsCarveoutSizeMb = 0x00000000,
+ .McMtsCarveoutRegCtrl = 0x00000000,
+},
diff --git a/src/mainboard/google/nyan/bct/sdram-unused.inc b/src/mainboard/google/nyan/bct/sdram-unused.inc
new file mode 100644
index 0000000000..bef63dcecc
--- /dev/null
+++ b/src/mainboard/google/nyan/bct/sdram-unused.inc
@@ -0,0 +1,4 @@
+{ /* dummy. */
+ .MemoryType = NvBootMemoryType_Unused,
+ 0,
+},
diff --git a/src/mainboard/google/nyan/bootblock.c b/src/mainboard/google/nyan/bootblock.c
index 0761aedb7b..c168550541 100644
--- a/src/mainboard/google/nyan/bootblock.c
+++ b/src/mainboard/google/nyan/bootblock.c
@@ -72,17 +72,19 @@ void bootblock_mainboard_init(void)
pmic_init(4);
/* SPI4 data out (MOSI) */
- pinmux_set_config(PINMUX_SDMMC1_CMD_INDEX,
- PINMUX_SDMMC1_CMD_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
+ pinmux_set_config(PINMUX_GPIO_PG6_INDEX,
+ PINMUX_GPIO_PG6_FUNC_SPI4 | PINMUX_INPUT_ENABLE |
+ PINMUX_PULL_UP);
/* SPI4 data in (MISO) */
- pinmux_set_config(PINMUX_SDMMC1_DAT1_INDEX,
- PINMUX_SDMMC1_DAT1_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
+ pinmux_set_config(PINMUX_GPIO_PG7_INDEX,
+ PINMUX_GPIO_PG7_FUNC_SPI4 | PINMUX_INPUT_ENABLE |
+ PINMUX_PULL_UP);
/* SPI4 clock */
- pinmux_set_config(PINMUX_SDMMC1_DAT2_INDEX,
- PINMUX_SDMMC1_DAT2_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
+ pinmux_set_config(PINMUX_GPIO_PG5_INDEX,
+ PINMUX_GPIO_PG5_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
/* SPI4 chip select 0 */
- pinmux_set_config(PINMUX_SDMMC1_DAT3_INDEX,
- PINMUX_SDMMC1_DAT3_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
+ pinmux_set_config(PINMUX_GPIO_PI3_INDEX,
+ PINMUX_GPIO_PI3_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
tegra_spi_init(4);
}
diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c
index ea40388823..3eaf38cf34 100644
--- a/src/mainboard/google/nyan/romstage.c
+++ b/src/mainboard/google/nyan/romstage.c
@@ -25,15 +25,12 @@
#include <cbfs.h>
#include <cbmem.h>
#include <console/console.h>
+#include "sdram_configs.h"
#include "soc/nvidia/tegra124/chip.h"
+#include "soc/nvidia/tegra124/sdram.h"
#include <soc/display.h>
#include <timestamp.h>
-// Convenient shorthand (in MB)
-#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20)
-#define DRAM_SIZE CONFIG_DRAM_SIZE_MB
-#define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */
-
enum {
L2CTLR_ECC_PARITY = 0x1 << 21,
L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6,
@@ -74,6 +71,7 @@ static void configure_l2actlr(void)
void main(void)
{
+ int dram_size_mb;
#if CONFIG_COLLECT_TIMESTAMPS
uint64_t romstage_start_time = timestamp_get();
#endif
@@ -97,12 +95,20 @@ void main(void)
console_init();
exception_init();
+ sdram_init(get_sdram_config());
+
+ /* used for MMU and CBMEM setup */
+ dram_size_mb = sdram_size_mb();
+
+ u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20);
+ u32 dram_end = dram_start + dram_size_mb; /* plus one... */
+
mmu_init();
- mmu_config_range(0, DRAM_START, DCACHE_OFF);
- mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
+ mmu_config_range(0, dram_start, DCACHE_OFF);
+ mmu_config_range(dram_start, dram_size_mb, DCACHE_WRITEBACK);
mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
- mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF);
+ mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
mmu_disable_range(0, 1);
dcache_invalidate_all();
dcache_mmu_enable();
diff --git a/src/mainboard/google/nyan/sdram_configs.c b/src/mainboard/google/nyan/sdram_configs.c
new file mode 100644
index 0000000000..89e33618fe
--- /dev/null
+++ b/src/mainboard/google/nyan/sdram_configs.c
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <soc/nvidia/tegra124/sdram.h>
+#include "sdram_configs.h"
+
+static struct sdram_params sdram_configs[] = {
+#include "bct/sdram-hynix-2GB-792.inc" /* ram_code = 0000 */
+#include "bct/sdram-unused.inc" /* ram_code = 0001 */
+#include "bct/sdram-unused.inc" /* ram_code = 0010 */
+#include "bct/sdram-unused.inc" /* ram_code = 0011 */
+#include "bct/sdram-unused.inc" /* ram_code = 0100 */
+#include "bct/sdram-unused.inc" /* ram_code = 0101 */
+#include "bct/sdram-unused.inc" /* ram_code = 0110 */
+#include "bct/sdram-unused.inc" /* ram_code = 0111 */
+#include "bct/sdram-unused.inc" /* ram_code = 1000 */
+#include "bct/sdram-unused.inc" /* ram_code = 1001 */
+#include "bct/sdram-unused.inc" /* ram_code = 1010 */
+#include "bct/sdram-unused.inc" /* ram_code = 1011 */
+#include "bct/sdram-unused.inc" /* ram_code = 1100 */
+#include "bct/sdram-unused.inc" /* ram_code = 1101 */
+#include "bct/sdram-unused.inc" /* ram_code = 1110 */
+#include "bct/sdram-unused.inc" /* ram_code = 1111 */
+};
+
+const struct sdram_params *get_sdram_config()
+{
+ uint32_t ramcode = sdram_get_ram_code();
+ /*
+ * If we need to apply some special hacks to RAMCODE mapping (ex, by
+ * board_id), do that now.
+ */
+
+ printk(BIOS_SPEW, "%s: RAMCODE=%d\n", __func__, ramcode);
+ if (ramcode >= sizeof(sdram_configs) / sizeof(sdram_configs[0]) ||
+ sdram_configs[ramcode].MemoryType == NvBootMemoryType_Unused) {
+ die("Invalid RAMCODE.");
+ }
+
+ return &sdram_configs[ramcode];
+}
diff --git a/src/mainboard/google/nyan/sdram_configs.h b/src/mainboard/google/nyan/sdram_configs.h
new file mode 100644
index 0000000000..e0ea1e285e
--- /dev/null
+++ b/src/mainboard/google/nyan/sdram_configs.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __MAINBOARD_GOOGLE_NYAN_SDRAM_CONFIG_H__
+#define __MAINBOARD_GOOGLE_NYAN_SDRAM_CONFIG_H__
+
+#include <soc/nvidia/tegra124/sdram_param.h>
+
+/* Loads SDRAM configurations for current system. */
+const struct sdram_params *get_sdram_config(void);
+
+#endif /* __MAINBOARD_GOOGLE_NYAN_SDRAM_CONFIG_H__ */
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