diff options
| author | Gabe Black <gabeblack@google.com> | 2014-02-08 05:17:38 -0800 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2014-11-12 02:25:31 +0100 |
| commit | 5cbbc702456ceab01b52bda49a2b991fde1658e7 (patch) | |
| tree | 65ab30a8c7720a013613594dd5ee5289952434bc /src/mainboard/google/nyan_big | |
| parent | f220df6ff9876fdc3f9e3abc08f0965ac4f55814 (diff) | |
| download | coreboot-5cbbc702456ceab01b52bda49a2b991fde1658e7.tar.xz | |
tegra124: nyan: Keep in memory structures below 4GB.
We'd been putting some data structures like the framebuffer and the cbmem at
the end of memory, but that may not actually be addressable as identity mapped
memory. This change clamps the addresses those structures are placed at so
they stay below 4GB.
BUG=None
TEST=Booted on nyan. Went into recovery mode and verified that there was a
recovery screen. Forced memory size to be 4GB and verified that the recovery
screen still shows up.
BRANCH=None
Original-Change-Id: I9e6b28212c113107d4f480b3dd846dd2349b3a91
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/185571
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 63ea1274a838dc739d302d7551f1db42034c5bd0)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I970c1285270cb648bc67fa114d44c0841eab1615
Reviewed-on: http://review.coreboot.org/7397
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/google/nyan_big')
| -rw-r--r-- | src/mainboard/google/nyan_big/romstage.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c index 9c887a82e8..c18138ae90 100644 --- a/src/mainboard/google/nyan_big/romstage.c +++ b/src/mainboard/google/nyan_big/romstage.c @@ -71,7 +71,6 @@ static void configure_l2actlr(void) static void __attribute__((noinline)) romstage(void) { - int dram_size_mb; #if CONFIG_COLLECT_TIMESTAMPS uint64_t romstage_start_time = timestamp_get(); #endif @@ -84,15 +83,14 @@ static void __attribute__((noinline)) romstage(void) sdram_init(get_sdram_config()); - /* used for MMU and CBMEM setup */ - dram_size_mb = sdram_size_mb(); - + /* used for MMU and CBMEM setup, in MB */ u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20); - u32 dram_end = dram_start + dram_size_mb; /* plus one... */ + u32 dram_end = sdram_max_addressable_mb(); /* plus one... */ + u32 dram_size = dram_end - dram_start; mmu_init(); mmu_config_range(0, dram_start, DCACHE_OFF); - mmu_config_range(dram_start, dram_size_mb, DCACHE_WRITEBACK); + mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK); mmu_config_range(CONFIG_DRAM_DMA_START >> 20, CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF); mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF); |