summaryrefslogtreecommitdiff
path: root/src/mainboard/google/nyan_big
diff options
context:
space:
mode:
authorJimmy Zhang <jimmzhang@nvidia.com>2014-03-10 12:42:05 -0700
committerMarc Jones <marc.jones@se-eng.com>2014-11-14 07:27:17 +0100
commitbd5925ab2dfb5bcdecba539b83827d7788bc6808 (patch)
treea2a508884d63c2059a9e8ae363238bb99da77bad /src/mainboard/google/nyan_big
parent4e16a2ea17a1b104507aeed8fca9c35750728248 (diff)
downloadcoreboot-bd5925ab2dfb5bcdecba539b83827d7788bc6808.tar.xz
t124: Clean up display init functions
The existing display init functions were translated from a script. The new code will play the same functions but are cleaner and readable and easier to be ported to new panel. BUG=none TEST=build nyan and boot up kernel. Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Change-Id: Ic9983e57684a03e206efe3731968ec62905f4ee8 Original-Reviewed-on: https://chromium-review.googlesource.com/189518 Original-Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com> Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 5998f991ea3069d603443b93c2ebdcdcd04af961) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Squashed to pass abuild nyan: Fix the build for big and blaze. The display code for the tegra124 was cleaned up recently, but only the nyan device tree was updated to match the new code, not big's or blaze's. This change copies nyan's device tree over to those other two boards which will get them building again. The settings may not be correct, but they'll be no less correct than they were before. I also updated the copyright date for nyan. BUG=none TEST=Built for nyan, nyan_big, nyan_blaze. Booted on nyan_big and verified the panel wasn't damaged by the new display code or settings. BRANCH=None Original-Change-Id: I75055a01f9402b3a9de9a787a9d3e737d25bb515 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/191364 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit ea235f23df31b4ca8006dcdf3628eed096e062b9) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Icdad74bf2d013c3677e1a3373b8f89fad99f616e Reviewed-on: http://review.coreboot.org/7454 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
Diffstat (limited to 'src/mainboard/google/nyan_big')
-rw-r--r--src/mainboard/google/nyan_big/devicetree.cb59
1 files changed, 40 insertions, 19 deletions
diff --git a/src/mainboard/google/nyan_big/devicetree.cb b/src/mainboard/google/nyan_big/devicetree.cb
index 9541ce9c9d..bf6c7f3bb3 100644
--- a/src/mainboard/google/nyan_big/devicetree.cb
+++ b/src/mainboard/google/nyan_big/devicetree.cb
@@ -28,9 +28,14 @@ chip soc/nvidia/tegra124
register "display_controller" = "TEGRA_ARM_DISPLAYA"
register "xres" = "1366"
register "yres" = "768"
- # this setting is what nvidia does; it makes no sense
- # and does not agree with hardware. Why'd they do it?
- register "framebuffer_bits_per_pixel" = "18"
+
+ # bits per pixel and color depth
+ register "framebuffer_bits_per_pixel" = "16"
+ register "color_depth" = "6"
+ # "6" is defined as COLOR_DEPTH_B5G6R5 in dc_reg.h
+
+ register "panel_bits_per_pixel" = "18"
+
register "cache_policy" = "DCACHE_WRITETHROUGH"
# With some help from the mainbaord designer
@@ -40,12 +45,12 @@ chip soc/nvidia/tegra124
register "panel_vdd_gpio" = "0"
register "pwm" = "1"
-# taken from u-boot; these look wrong however.
- register "vdd_delay" = "400"
- register "vdd_data_delay" = "4"
- register "data_backlight_delay" = "203"
- register "backlight_pwm_delay" = "17"
- register "pwm_backlight_en_delay" = "15"
+ # various panel delay time
+ register "vdd_delay_ms" = "200"
+ register "vdd_to_hpd_delay_ms" = "200"
+ register "hpd_unplug_min_us" = "2000"
+ register "hpd_plug_min_us" = "250"
+ register "hpd_irq_min_us" = "250"
# How to compute these: xrandr --verbose will give you this:
#Detailed mode: Clock 285.250 MHz, 272 mm x 181 mm
@@ -64,17 +69,33 @@ chip soc/nvidia/tegra124
# 1366x768 (0x45) 76.4MHz -HSync -VSync *current +preferred
# h: width 1366 start 1502 end 1532 total 1592
# v: height 768 start 776 end 788 total 800
-# These numbers were provided by Nvidia.
- register "href_to_sync" = "1"
- register "hfront_porch" = "44"
- register "hsync_width" = "46"
- register "hback_porch" = "44"
+ register "href_to_sync" = "68"
+ register "hfront_porch" = "136"
+ register "hsync_width" = "30"
+ register "hback_porch" = "60"
- register "vref_to_sync" = "1"
- register "vfront_porch" = "6"
- register "vsync_width" = "8"
- register "vback_porch" = "6"
+ register "vref_to_sync" = "4"
+ register "vfront_porch" = "8"
+ register "vsync_width" = "12"
+ register "vback_porch" = "12"
# we *know* the pixel clock for this system.
- register "pixel_clock" = "71"
+ # 1592 x 800 x 60Hz = 76416000
+ register "pixel_clock" = "76416000"
+ register "pll_div" = "2"
+
+ # use plld_out0 (ie, plld/2) as clock source
+ # plld -> plld_out0 -> pclk
+ # plld = plld_out0 * 2 = (pclk * pll_div) * 2
+ # = 305664000Hz
+
+ # link configurations
+ register "lane_count" = "1"
+ register "enhanced_framing" = "1"
+ register "link_bw" = "10"
+ # "10" is defined as SOR_LINK_SPEED_G2_7 in sor.h
+
+ register "drive_current" = "0x13131313"
+ register "preemphasis" = "0x00000000"
+ register "postcursor" = "0"
end