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authorGabe Black <gabeblack@google.com>2014-02-08 05:01:06 -0800
committerMarc Jones <marc.jones@se-eng.com>2014-11-12 02:25:06 +0100
commitf220df6ff9876fdc3f9e3abc08f0965ac4f55814 (patch)
tree5de42ed1892e5a3892c3a48aee4ca02cf569547e /src/mainboard/google/nyan_big
parent1dba8787c65e2bbb781cd204c5084dee797d2994 (diff)
downloadcoreboot-f220df6ff9876fdc3f9e3abc08f0965ac4f55814.tar.xz
nyan: Use asm volatile instead of plain asm so it doesn't get optimized out.
If an asm blob isn't marked as volatile, gcc is free to throw it out if it doesn't think it produces any values that are actually used. To prevent that from happening, add volatile to some asm blobs in the nyan romstage code. BUG=None TEST=Booted on nyan rev1. BRANCH=None Original-Change-Id: I819e068e738e94ea749fcb72bba2eee080e1dfb1 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/185610 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 76c09581d6ca4dc6c2f9048f599822939f439d11) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I0b32197abf0ddc5f454f9c2415a65d98c60ca48b Reviewed-on: http://review.coreboot.org/7396 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/google/nyan_big')
-rw-r--r--src/mainboard/google/nyan_big/romstage.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c
index 5fd255e104..9c887a82e8 100644
--- a/src/mainboard/google/nyan_big/romstage.c
+++ b/src/mainboard/google/nyan_big/romstage.c
@@ -136,6 +136,7 @@ static void __attribute__((noinline)) romstage(void)
/* Stub to force arm_init_caches to the top, before any stack/memory accesses */
void main(void)
{
- asm ("bl arm_init_caches" ::: "r0","r1","r2","r3","r4","r5","ip");
+ asm volatile ("bl arm_init_caches"
+ ::: "r0","r1","r2","r3","r4","r5","ip");
romstage();
}