diff options
author | Tom Warren <twarren@nvidia.com> | 2014-03-19 14:19:09 -0700 |
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committer | Marc Jones <marc.jones@se-eng.com> | 2014-11-14 07:27:06 +0100 |
commit | 4e16a2ea17a1b104507aeed8fca9c35750728248 (patch) | |
tree | 9c5d36460eddd73a282b0ff98e4a8f0824a09150 /src/mainboard/google/nyan_blaze/romstage.c | |
parent | 764cd1bb3aa7733dbaaabc5b42ec096960975d5b (diff) | |
download | coreboot-4e16a2ea17a1b104507aeed8fca9c35750728248.tar.xz |
blaze: Create a nyan_blaze mainboard, copied from nyan_big
The nyan_blaze board will have different BCT .inc files, to be
added/updated later. GPIOs and some devicetree stuff may also differ.
BUG=None
TEST=Built nyan, nyan_big and nyan_blaze.
BRANCH=None
Original-Change-Id: I8b16fc71346cf973983aa046096b79cb83ad4bb6
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/190721
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit bea753131e2247a90cc5359fa5f603026d66c7ce)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I435ae78da2f6c4f1a78fea8300b6285e52272535
Reviewed-on: http://review.coreboot.org/7453
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Diffstat (limited to 'src/mainboard/google/nyan_blaze/romstage.c')
-rw-r--r-- | src/mainboard/google/nyan_blaze/romstage.c | 147 |
1 files changed, 147 insertions, 0 deletions
diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c new file mode 100644 index 0000000000..51f5a49264 --- /dev/null +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -0,0 +1,147 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/cache.h> +#include <arch/cpu.h> +#include <arch/exception.h> +#include <arch/stages.h> +#include <device/device.h> +#include <cbfs.h> +#include <cbmem.h> +#include <console/console.h> +#include "sdram_configs.h" +#include "soc/nvidia/tegra124/chip.h" +#include "soc/nvidia/tegra124/sdram.h" +#include <soc/display.h> +#include <timestamp.h> + +enum { + L2CTLR_ECC_PARITY = 0x1 << 21, + L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6, + L2CTLR_TAG_RAM_LATENCY_CYCLES_3 = 2 << 6, + L2CTLR_DATA_RAM_LATENCY_MASK = 0x7 << 0, + L2CTLR_DATA_RAM_LATENCY_CYCLES_3 = 2 << 0 +}; + +enum { + L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE = 0x1 << 27, + L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT = 0x1 << 7, + L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL = 0x1 << 3 +}; + +/* Configures L2 Control Register to use 3 cycles for DATA/TAG RAM latency. */ +static void configure_l2ctlr(void) +{ + uint32_t val; + + val = read_l2ctlr(); + val &= ~(L2CTLR_DATA_RAM_LATENCY_MASK | L2CTLR_TAG_RAM_LATENCY_MASK); + val |= (L2CTLR_DATA_RAM_LATENCY_CYCLES_3 | L2CTLR_TAG_RAM_LATENCY_CYCLES_3 | + L2CTLR_ECC_PARITY); + write_l2ctlr(val); +} + +/* Configures L2 Auxiliary Control Register for Cortex A15. */ +static void configure_l2actlr(void) +{ + uint32_t val; + + val = read_l2actlr(); + val |= (L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL | + L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT | + L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE); + write_l2actlr(val); +} + +static void __attribute__((noinline)) romstage(void) +{ +#if CONFIG_COLLECT_TIMESTAMPS + uint64_t romstage_start_time = timestamp_get(); +#endif + + configure_l2ctlr(); + configure_l2actlr(); + + console_init(); + exception_init(); + + sdram_init(get_sdram_config()); + + /* used for MMU and CBMEM setup, in MB */ + u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20); + u32 dram_end = sdram_max_addressable_mb(); /* plus one... */ + u32 dram_size = dram_end - dram_start; + + mmu_init(); + /* Device memory below DRAM is uncached. */ + mmu_config_range(0, dram_start, DCACHE_OFF); + /* SRAM is cached. Round the size up to 2MB, the LPAE page size. */ + mmu_config_range(0x40000000 >> 20, 2, DCACHE_WRITEBACK); + /* DRAM is cached. */ + mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK); + /* A window for DMA is uncached. */ + mmu_config_range(CONFIG_DRAM_DMA_START >> 20, + CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF); + /* The space above DRAM is uncached. */ + if (dram_end < 4096) + mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF); + mmu_disable_range(0, 1); + dcache_mmu_enable(); + + /* For quality of the user experience, it's important to get + * the video going ASAP. Because there are long delays in some + * of the powerup steps, we do some very early setup here in + * romstage. The only thing setup_display does is manage + * 4 GPIOs, under control of the config struct members. + * In general, it is safe to enable panel power, and disable + * anything related to the backlight. If we get something wrong, + * we can easily fix it in ramstage by further GPIO manipulation, + * so we feel it is ok to do some setting at this point. + */ + + const struct device *soc = dev_find_slot(DEVICE_PATH_CPU_CLUSTER, 0); + printk(BIOS_SPEW, "s%s: soc is %p\n", __func__, soc); + if (soc && soc->chip_info) { + const struct soc_nvidia_tegra124_config *config = + soc->chip_info; + setup_display((struct soc_nvidia_tegra124_config *)config); + } + + cbmem_initialize_empty(); + +#if CONFIG_COLLECT_TIMESTAMPS + timestamp_init(0); + timestamp_add(TS_START_ROMSTAGE, romstage_start_time); + timestamp_add(TS_START_COPYRAM, timestamp_get()); +#endif + void *entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, + "fallback/coreboot_ram"); +#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add(TS_END_COPYRAM, timestamp_get()); +#endif + stage_exit(entry); +} + +/* Stub to force arm_init_caches to the top, before any stack/memory accesses */ +void main(void) +{ + asm volatile ("bl arm_init_caches" + ::: "r0","r1","r2","r3","r4","r5","ip"); + romstage(); +} |