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| author | Aaron Durbin <adurbin@chromium.org> | 2015-04-22 10:41:42 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-28 16:09:56 +0200 |
| commit | 1124cec59a2c705a4ef3740dbdf0f68113602d31 (patch) | |
| tree | e5c519b0539e581c05c9d9f610a1a6deea9cd3a6 /src/mainboard/google/nyan_blaze/romstage.c | |
| parent | 6d65f796db04927bfc8324f50ad0816cec9673b6 (diff) | |
| download | coreboot-1124cec59a2c705a4ef3740dbdf0f68113602d31.tar.xz | |
chromeos: remove VBOOT2_VERIFY_FIRMWARE option
There's no need to have the VBOOT2_VERIFY_FIRMWARE
distinction because it's the only game in town.
Change-Id: I82aab665934c27829e1a04115bf499ae527a91aa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9958
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/google/nyan_blaze/romstage.c')
| -rw-r--r-- | src/mainboard/google/nyan_blaze/romstage.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c index c9510d627e..12b2ffb366 100644 --- a/src/mainboard/google/nyan_blaze/romstage.c +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -58,7 +58,7 @@ static void __attribute__((noinline)) romstage(void) u32 dram_end_mb = sdram_max_addressable_mb(); u32 dram_size_mb = dram_end_mb - dram_start_mb; -#if !CONFIG_VBOOT2_VERIFY_FIRMWARE +#if !CONFIG_VBOOT_VERIFY_FIRMWARE configure_l2_cache(); mmu_init(); /* Device memory below DRAM is uncached. */ @@ -95,7 +95,7 @@ static void __attribute__((noinline)) romstage(void) early_mainboard_init(); -#if CONFIG_VBOOT2_VERIFY_FIRMWARE +#if CONFIG_VBOOT_VERIFY_FIRMWARE entry = vboot2_load_ramstage(); #else early_mainboard_init(); @@ -108,7 +108,7 @@ static void __attribute__((noinline)) romstage(void) /* Stub to force arm_init_caches to the top, before any stack/memory accesses */ void main(void) { -#if !CONFIG_VBOOT2_VERIFY_FIRMWARE +#if !CONFIG_VBOOT_VERIFY_FIRMWARE asm volatile ("bl arm_init_caches" ::: "r0","r1","r2","r3","r4","r5","ip"); #endif |