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authorJulius Werner <jwerner@chromium.org>2015-02-19 14:51:15 -0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-21 08:22:28 +0200
commit2f37bd65518865688b9234afce0d467508d6f465 (patch)
treeeba5ed799de966299602b30c70d51dd40eaadd73 /src/mainboard/google/nyan_blaze
parent1f60f971fc89ef841e81b978964b38278d597b1d (diff)
downloadcoreboot-2f37bd65518865688b9234afce0d467508d6f465.tar.xz
arm(64): Globally replace writel(v, a) with write32(a, v)
This patch is a raw application of the following spatch to src/: @@ expression A, V; @@ - writel(V, A) + write32(A, V) @@ expression A, V; @@ - writew(V, A) + write16(A, V) @@ expression A, V; @@ - writeb(V, A) + write8(A, V) @@ expression A; @@ - readl(A) + read32(A) @@ expression A; @@ - readb(A) + read8(A) BRANCH=none BUG=chromium:444723 TEST=None (depends on next patch) Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6 Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254864 Reviewed-on: http://review.coreboot.org/9836 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/nyan_blaze')
-rw-r--r--src/mainboard/google/nyan_blaze/bootblock.c2
-rw-r--r--src/mainboard/google/nyan_blaze/mainboard.c8
2 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/google/nyan_blaze/bootblock.c b/src/mainboard/google/nyan_blaze/bootblock.c
index c471cb841a..94943974d1 100644
--- a/src/mainboard/google/nyan_blaze/bootblock.c
+++ b/src/mainboard/google/nyan_blaze/bootblock.c
@@ -36,7 +36,7 @@ static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
static void set_clock_sources(void)
{
/* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */
- writel(PLLP << CLK_SOURCE_SHIFT, &clk_rst->clk_src_uarta);
+ write32(&clk_rst->clk_src_uarta, PLLP << CLK_SOURCE_SHIFT);
clock_configure_source(mselect, PLLP, 102000);
diff --git a/src/mainboard/google/nyan_blaze/mainboard.c b/src/mainboard/google/nyan_blaze/mainboard.c
index 9daa2bb6b3..f5aa1393f1 100644
--- a/src/mainboard/google/nyan_blaze/mainboard.c
+++ b/src/mainboard/google/nyan_blaze/mainboard.c
@@ -184,13 +184,13 @@ static void setup_kernel_info(void)
// from CONFIG_CONSOLE_SERIAL_UART[A-E]. Right now we simply copy the
// value defined in BCT.
struct tegra_pmc_regs *pmc = (void*)TEGRA_PMC_BASE;
- writel(0x80080000, &pmc->odmdata);
+ write32(&pmc->odmdata, 0x80080000);
// Not strictly info, but kernel graphics driver needs this region locked down
struct tegra_mc_regs *mc = (void *)TEGRA_MC_BASE;
- writel(0, &mc->video_protect_bom);
- writel(0, &mc->video_protect_size_mb);
- writel(1, &mc->video_protect_reg_ctrl);
+ write32(&mc->video_protect_bom, 0);
+ write32(&mc->video_protect_size_mb, 0);
+ write32(&mc->video_protect_reg_ctrl, 1);
}
static void setup_ec_spi(void)