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authorJulius Werner <jwerner@chromium.org>2014-11-20 17:02:17 -0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-13 13:03:01 +0200
commit36fd82dfc4523adc08cce5d553b8ae8575e77ab5 (patch)
treee0f5c6194967aaf1ddf3e7a4341ad09e19272c26 /src/mainboard/google/nyan_blaze
parent3d28479cb161329a5a5bab5e6c005287e0d003e6 (diff)
downloadcoreboot-36fd82dfc4523adc08cce5d553b8ae8575e77ab5.tar.xz
nyan/rush/veyron: Align ChromeOS GPIOs to new model
This CL makes slight changes to the ChromeOS-specific GPIO definitions of Tegra and Rockchip boards to prepare them for new features in depthcharge. It adds descriptions for the EC in RW and reset GPIOs, changes the value Tegra writes into the (previously unused) 'port' field to describe the complete GPIO information, and removes code to sample some GPIOs that don't need to be sampled at coreboot time (to help depthcharge detect errors and avoid using a stale value for something that should always represent the current state). BRANCH=None BUG=None TEST=None (tested together with depthcharge patches) Change-Id: I3774979dbe7cacce4932c85810596d80e5664028 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: df295d0432fbf623597cf36ebb170bd4f63ee08d Original-Change-Id: I36bb16c8d931f862bf12a5b862b10cf18d738ddd Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/231222 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9570 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/google/nyan_blaze')
-rw-r--r--src/mainboard/google/nyan_blaze/chromeos.c26
1 files changed, 21 insertions, 5 deletions
diff --git a/src/mainboard/google/nyan_blaze/chromeos.c b/src/mainboard/google/nyan_blaze/chromeos.c
index 7718849fe8..4c72eabb64 100644
--- a/src/mainboard/google/nyan_blaze/chromeos.c
+++ b/src/mainboard/google/nyan_blaze/chromeos.c
@@ -35,7 +35,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int count = 0;
/* Write Protect: active low */
- gpios->gpios[count].port = GPIO_R1_INDEX;
+ gpios->gpios[count].port = GPIO(R1);
gpios->gpios[count].polarity = ACTIVE_LOW;
gpios->gpios[count].value = gpio_get(GPIO(R1));
strncpy((char *)gpios->gpios[count].name, "write protect",
@@ -51,16 +51,16 @@ void fill_lb_gpios(struct lb_gpios *gpios)
count++;
/* Lid: active high */
- gpios->gpios[count].port = GPIO_R4_INDEX;
+ gpios->gpios[count].port = GPIO(R4);
gpios->gpios[count].polarity = ACTIVE_HIGH;
- gpios->gpios[count].value = gpio_get(GPIO(R4));
+ gpios->gpios[count].value = -1;
strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH);
count++;
/* Power: active low */
- gpios->gpios[count].port = GPIO_Q0_INDEX;
+ gpios->gpios[count].port = GPIO(Q0);
gpios->gpios[count].polarity = ACTIVE_LOW;
- gpios->gpios[count].value = gpio_get(GPIO(Q0));
+ gpios->gpios[count].value = -1;
strncpy((char *)gpios->gpios[count].name, "power",
GPIO_MAX_NAME_LENGTH);
count++;
@@ -73,6 +73,22 @@ void fill_lb_gpios(struct lb_gpios *gpios)
GPIO_MAX_NAME_LENGTH);
count++;
+ /* EC in RW: active high */
+ gpios->gpios[count].port = GPIO(U4);
+ gpios->gpios[count].polarity = ACTIVE_HIGH;
+ gpios->gpios[count].value = -1;
+ strncpy((char *)gpios->gpios[count].name, "EC in RW",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ /* Reset: active low (output) */
+ gpios->gpios[count].port = GPIO(I5);
+ gpios->gpios[count].polarity = ACTIVE_LOW;
+ gpios->gpios[count].value = -1;
+ strncpy((char *)gpios->gpios[count].name, "reset",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio));
gpios->count = count;