summaryrefslogtreecommitdiff
path: root/src/mainboard/google/nyan_blaze
diff options
context:
space:
mode:
authorElyes HAOUAS <ehaouas@noos.fr>2018-11-26 22:53:49 +0100
committerPatrick Georgi <pgeorgi@google.com>2018-11-29 12:17:45 +0000
commit6df3b64c77a868ab8526b980561ed2be3fe392b6 (patch)
treea95ac78c1e4e222971ee9749e9e114494681e9c4 /src/mainboard/google/nyan_blaze
parent1a5ce95815210032783d01e830390ee5b6a54dc5 (diff)
downloadcoreboot-6df3b64c77a868ab8526b980561ed2be3fe392b6.tar.xz
src: Remove duplicated round up function
This removes CEIL_DIV and div_round_up() altogether and replace it by DIV_ROUND_UP defined in commonlib/helpers.h. Change-Id: I9aabc3fbe7834834c92d6ba59ff0005986622a34 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/mainboard/google/nyan_blaze')
-rw-r--r--src/mainboard/google/nyan_blaze/romstage.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c
index 602989df27..e44381f238 100644
--- a/src/mainboard/google/nyan_blaze/romstage.c
+++ b/src/mainboard/google/nyan_blaze/romstage.c
@@ -57,7 +57,7 @@ static void __attribute__((noinline)) romstage(void)
/* Device memory below DRAM is uncached. */
mmu_config_range(0, dram_start_mb, DCACHE_OFF);
/* SRAM is cached. MMU code will round size up to page size. */
- mmu_config_range((uintptr_t)_sram/MiB, div_round_up(_sram_size, MiB),
+ mmu_config_range((uintptr_t)_sram/MiB, DIV_ROUND_UP(_sram_size, MiB),
DCACHE_WRITEBACK);
/* The space above DRAM is uncached. */
if (dram_end_mb < 4096)