diff options
| author | Gabe Black <gabeblack@google.com> | 2014-03-26 21:58:06 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2014-11-14 07:28:26 +0100 |
| commit | b19136ff0ba0b72e2bb273dc4660157533f651f3 (patch) | |
| tree | ac6b30690984402b0801182a794ed1408361dae2 /src/mainboard/google/nyan_blaze | |
| parent | 6541b283b056fc7f8b0752508c8b3babb5b53e33 (diff) | |
| download | coreboot-b19136ff0ba0b72e2bb273dc4660157533f651f3.tar.xz | |
nyan: tpm: Increase the TPM frequency to 400 KHz.
The TPM now works correctly with the I2C bus running at 400 KHz. Running it at
that frequency saves some boot time.
CQ-DEPEND=CL:191634
CQ-DEPEND=CL:191793
BUG=chrome-os-partner:27220
TEST=Built and booted on nyan with and without EFS.
BRANCH=None
Original-Change-Id: I157308c2745342dc1ada4499433004c7ce1c6435
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/191813
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 39a740d488d8f33ee698805bc2a8438263162cc8)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I02978407e20cc9d526545157a3a3304729a91010
Reviewed-on: http://review.coreboot.org/7461
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/google/nyan_blaze')
| -rw-r--r-- | src/mainboard/google/nyan_blaze/romstage.c | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c index e1597c8ba9..6327c97ba3 100644 --- a/src/mainboard/google/nyan_blaze/romstage.c +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -134,12 +134,7 @@ static void configure_ec_spi_bus(void) static void configure_tpm_i2c_bus(void) { - /* - * The TPM is on I2C3 and can theoretically run at 400 KHz but doesn't - * seem to work above around 40 KHz. It's set to run at 100 KHz in the - * kernel. - */ - clock_configure_i2c_scl_freq(i2c3, PLLP, 40); + clock_configure_i2c_scl_freq(i2c3, PLLP, 400); i2c_init(2); } |