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authorMengqi Zhang <Mengqi.Zhang@mediatek.com>2019-04-24 11:11:52 +0800
committerPatrick Georgi <pgeorgi@google.com>2019-06-21 08:38:41 +0000
commit026be3d76f3934eb901485acd98e0d84f137068f (patch)
treec269b874ad1fccd60889cc0fac94dd1f746608a7 /src/mainboard/google/oak/bootblock.c
parent89b1753c2289edacca05ef46e840f212f2a3025d (diff)
downloadcoreboot-026be3d76f3934eb901485acd98e0d84f137068f.tar.xz
mediatek: Add SPI tick_dly setting
Add spi tick_dly setting for high-speed spi xfer. BUG=b:80501386 BRANCH=none TEST=emerge-kukui coreboot; emerge-elm coreboot Change-Id: Ie49fc3efe2a4a6dcdf2a2fc4c91b47e35d4f086e Signed-off-by: Mengqi Zhang <Mengqi.Zhang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/mainboard/google/oak/bootblock.c')
-rw-r--r--src/mainboard/google/oak/bootblock.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c
index 3c50389914..89169ef0bf 100644
--- a/src/mainboard/google/oak/bootblock.c
+++ b/src/mainboard/google/oak/bootblock.c
@@ -89,7 +89,8 @@ void bootblock_mainboard_init(void)
if (CONFIG(OAK_HAS_TPM2))
gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING);
- mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD1_MASK, 6*MHz);
+ mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD1_MASK, 6*MHz,
+ 0);
setup_chromeos_gpios();