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authorTristan Shieh <tristan.shieh@mediatek.com>2018-07-09 18:59:32 +0800
committerPatrick Georgi <pgeorgi@google.com>2018-07-20 13:50:54 +0000
commit71d227b1085b5f54b11a6fcfa9419597ee5c9f56 (patch)
tree49ba7259011ef038a6b8f9aa1808523b650115fe /src/mainboard/google/oak/bootblock.c
parentccb62960db3eff2d4c2905710ba99ba90f24bcdc (diff)
downloadcoreboot-71d227b1085b5f54b11a6fcfa9419597ee5c9f56.tar.xz
mediatek: Share GPIO code among similar SOCs
Refactor GPIO code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: Icdd1f2a1dd1bd64a7218bf9c63bd4a0af1acbcc0 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/mainboard/google/oak/bootblock.c')
-rw-r--r--src/mainboard/google/oak/bootblock.c43
1 files changed, 21 insertions, 22 deletions
diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c
index fe9c9ba8c4..9cba3b4d23 100644
--- a/src/mainboard/google/oak/bootblock.c
+++ b/src/mainboard/google/oak/bootblock.c
@@ -22,17 +22,16 @@
#include <soc/i2c.h>
#include <soc/mt6391.h>
#include <soc/pericfg.h>
-#include <soc/pinmux.h>
#include <soc/spi.h>
#include "gpio.h"
static void i2c_set_gpio_pinmux(void)
{
- gpio_set_mode(PAD_SDA1, PAD_SDA1_FUNC_SDA1);
- gpio_set_mode(PAD_SCL1, PAD_SCL1_FUNC_SCL1);
- gpio_set_mode(PAD_SDA4, PAD_SDA4_FUNC_SDA4);
- gpio_set_mode(PAD_SCL4, PAD_SCL4_FUNC_SCL4);
+ gpio_set_mode(GPIO(SDA1), PAD_SDA1_FUNC_SDA1);
+ gpio_set_mode(GPIO(SCL1), PAD_SCL1_FUNC_SCL1);
+ gpio_set_mode(GPIO(SDA4), PAD_SDA4_FUNC_SDA4);
+ gpio_set_mode(GPIO(SCL4), PAD_SCL4_FUNC_SCL4);
}
static void nor_set_gpio_pinmux(void)
@@ -44,23 +43,23 @@ static void nor_set_gpio_pinmux(void)
* 3: 16mA
*/
/* EINT4: 0x10005B20[14:13] */
- clrsetbits_le16(&mt8173_gpio->drv_mode[2].val, 0xf << 12, 2 << 13);
+ clrsetbits_le16(&mtk_gpio->drv_mode[2].val, 0xf << 12, 2 << 13);
/* EINT5~EINT9: 0x10005B30[2:1] */
- clrsetbits_le16(&mt8173_gpio->drv_mode[3].val, 0xf << 0, 2 << 1),
-
- gpio_set_pull(PAD_EINT4, GPIO_PULL_ENABLE, GPIO_PULL_UP);
- gpio_set_pull(PAD_EINT5, GPIO_PULL_ENABLE, GPIO_PULL_UP);
- gpio_set_pull(PAD_EINT6, GPIO_PULL_ENABLE, GPIO_PULL_UP);
- gpio_set_pull(PAD_EINT7, GPIO_PULL_ENABLE, GPIO_PULL_UP);
- gpio_set_pull(PAD_EINT8, GPIO_PULL_ENABLE, GPIO_PULL_UP);
- gpio_set_pull(PAD_EINT9, GPIO_PULL_ENABLE, GPIO_PULL_UP);
-
- gpio_set_mode(PAD_EINT4, PAD_EINT4_FUNC_SFWP_B);
- gpio_set_mode(PAD_EINT5, PAD_EINT5_FUNC_SFOUT);
- gpio_set_mode(PAD_EINT6, PAD_EINT6_FUNC_SFCS0);
- gpio_set_mode(PAD_EINT7, PAD_EINT7_FUNC_SFHOLD);
- gpio_set_mode(PAD_EINT8, PAD_EINT8_FUNC_SFIN);
- gpio_set_mode(PAD_EINT9, PAD_EINT9_FUNC_SFCK);
+ clrsetbits_le16(&mtk_gpio->drv_mode[3].val, 0xf << 0, 2 << 1),
+
+ gpio_set_pull(GPIO(EINT4), GPIO_PULL_ENABLE, GPIO_PULL_UP);
+ gpio_set_pull(GPIO(EINT5), GPIO_PULL_ENABLE, GPIO_PULL_UP);
+ gpio_set_pull(GPIO(EINT6), GPIO_PULL_ENABLE, GPIO_PULL_UP);
+ gpio_set_pull(GPIO(EINT7), GPIO_PULL_ENABLE, GPIO_PULL_UP);
+ gpio_set_pull(GPIO(EINT8), GPIO_PULL_ENABLE, GPIO_PULL_UP);
+ gpio_set_pull(GPIO(EINT9), GPIO_PULL_ENABLE, GPIO_PULL_UP);
+
+ gpio_set_mode(GPIO(EINT4), PAD_EINT4_FUNC_SFWP_B);
+ gpio_set_mode(GPIO(EINT5), PAD_EINT5_FUNC_SFOUT);
+ gpio_set_mode(GPIO(EINT6), PAD_EINT6_FUNC_SFCS0);
+ gpio_set_mode(GPIO(EINT7), PAD_EINT7_FUNC_SFHOLD);
+ gpio_set_mode(GPIO(EINT8), PAD_EINT8_FUNC_SFIN);
+ gpio_set_mode(GPIO(EINT9), PAD_EINT9_FUNC_SFCK);
}
void bootblock_mainboard_early_init(void)
@@ -83,7 +82,7 @@ void bootblock_mainboard_init(void)
/* SPI_LEVEL_ENABLE: Enable 1.8V to 3.3V level shifter for EC SPI bus */
if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 4 &&
board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 8)
- gpio_output(PAD_SRCLKENAI2, 1);
+ gpio_output(GPIO(SRCLKENAI2), 1);
/* Init i2c bus 2 Timing register for TPM */
mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS);