diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-12-02 22:03:27 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-04 14:11:17 +0000 |
| commit | 55009af42c39f413c49503670ce9bc2858974962 (patch) | |
| tree | 099e9728bfe8066999de4d7a30021eb10bd71d12 /src/mainboard/google/oak/bootblock.c | |
| parent | 1c371572188a90ea16275460dd4ab6bf9966350b (diff) | |
| download | coreboot-55009af42c39f413c49503670ce9bc2858974962.tar.xz | |
Change all clrsetbits_leXX() to clrsetbitsXX()
This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.
This patch was created by running
sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'
across the codebase and cleaning up formatting a bit.
Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/mainboard/google/oak/bootblock.c')
| -rw-r--r-- | src/mainboard/google/oak/bootblock.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c index 89169ef0bf..73e50fda63 100644 --- a/src/mainboard/google/oak/bootblock.c +++ b/src/mainboard/google/oak/bootblock.c @@ -42,9 +42,9 @@ static void nor_set_gpio_pinmux(void) * 3: 16mA */ /* EINT4: 0x10005B20[14:13] */ - clrsetbits_le16(&mtk_gpio->drv_mode[2].val, 0xf << 12, 2 << 13); + clrsetbits16(&mtk_gpio->drv_mode[2].val, 0xf << 12, 2 << 13); /* EINT5~EINT9: 0x10005B30[2:1] */ - clrsetbits_le16(&mtk_gpio->drv_mode[3].val, 0xf << 0, 2 << 1), + clrsetbits16(&mtk_gpio->drv_mode[3].val, 0xf << 0, 2 << 1), gpio_set_pull(GPIO(EINT4), GPIO_PULL_ENABLE, GPIO_PULL_UP); gpio_set_pull(GPIO(EINT5), GPIO_PULL_ENABLE, GPIO_PULL_UP); @@ -64,7 +64,7 @@ static void nor_set_gpio_pinmux(void) void bootblock_mainboard_early_init(void) { /* Clear UART0 power down signal */ - clrbits_le32(&mt8173_pericfg->pdn0_set, PERICFG_UART0_PDN); + clrbits32(&mt8173_pericfg->pdn0_set, PERICFG_UART0_PDN); } void bootblock_mainboard_init(void) |