diff options
| author | Tristan Shieh <tristan.shieh@mediatek.com> | 2018-07-09 18:59:32 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-07-20 13:50:54 +0000 |
| commit | 71d227b1085b5f54b11a6fcfa9419597ee5c9f56 (patch) | |
| tree | 49ba7259011ef038a6b8f9aa1808523b650115fe /src/mainboard/google/oak/gpio.h | |
| parent | ccb62960db3eff2d4c2905710ba99ba90f24bcdc (diff) | |
| download | coreboot-71d227b1085b5f54b11a6fcfa9419597ee5c9f56.tar.xz | |
mediatek: Share GPIO code among similar SOCs
Refactor GPIO code which will be reused among similar SOCs.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Elm
Change-Id: Icdd1f2a1dd1bd64a7218bf9c63bd4a0af1acbcc0
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/mainboard/google/oak/gpio.h')
| -rw-r--r-- | src/mainboard/google/oak/gpio.h | 61 |
1 files changed, 30 insertions, 31 deletions
diff --git a/src/mainboard/google/oak/gpio.h b/src/mainboard/google/oak/gpio.h index 4bed95d546..666267170a 100644 --- a/src/mainboard/google/oak/gpio.h +++ b/src/mainboard/google/oak/gpio.h @@ -15,39 +15,38 @@ #ifndef __MAINBOARD_GOOGLE_OAK_GPIO_H__ #define __MAINBOARD_GOOGLE_OAK_GPIO_H__ -#include <soc/pinmux.h> +#include <soc/gpio.h> -#define LID ((IS_ENABLED(CONFIG_BOARD_GOOGLE_ROWAN)) ? PAD_KPROW1 \ - : ((board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 7) ? PAD_EINT12 \ - : PAD_SPI_CK)) +#if IS_ENABLED(CONFIG_BOARD_GOOGLE_ROWAN) +#define LID GPIO(KPROW1) +#define RAM_ID_1 GPIO(DSI_TE) +#define RAM_ID_2 GPIO(RDP1_A) +#else +#define LID ((board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 7) ? \ + GPIO(EINT12) : GPIO(SPI_CK)) +#define RAM_ID_1 GPIO(RCN_A) +#define RAM_ID_2 GPIO(RCP_A) +#endif -#define RAM_ID_1 ((IS_ENABLED(CONFIG_BOARD_GOOGLE_ROWAN)) ? PAD_DSI_TE \ - : PAD_RCN_A) - -#define RAM_ID_2 ((IS_ENABLED(CONFIG_BOARD_GOOGLE_ROWAN)) ? PAD_RDP1_A \ - : PAD_RCP_A) - -enum { - /* Board ID related GPIOS. */ - BOARD_ID_0 = PAD_RDN3_A, - BOARD_ID_1 = PAD_RDP3_A, - BOARD_ID_2 = PAD_RDN2_A, - /* RAM ID related GPIOS. */ - RAM_ID_0 = PAD_RDP2_A, - RAM_ID_3 = PAD_RDN1_A, - /* Write Protect */ - WRITE_PROTECT = PAD_EINT4, - /* Power button */ - POWER_BUTTON = PAD_EINT14, - /* EC Interrupt */ - EC_IRQ = PAD_EINT0, - /* EC in RW signal */ - EC_IN_RW = PAD_DAIPCMIN, - /* EC AP suspend */ - EC_SUSPEND_L = PAD_KPROW1, - /* Cr50 interrupt */ - CR50_IRQ = PAD_EINT16, -}; +/* Board ID related GPIOS. */ +#define BOARD_ID_0 GPIO(RDN3_A) +#define BOARD_ID_1 GPIO(RDP3_A) +#define BOARD_ID_2 GPIO(RDN2_A) +/* RAM ID related GPIOS. */ +#define RAM_ID_0 GPIO(RDP2_A) +#define RAM_ID_3 GPIO(RDN1_A) +/* Write Protect */ +#define WRITE_PROTECT GPIO(EINT4) +/* Power button */ +#define POWER_BUTTON GPIO(EINT14) +/* EC Interrupt */ +#define EC_IRQ GPIO(EINT0) +/* EC in RW signal */ +#define EC_IN_RW GPIO(DAIPCMIN) +/* EC AP suspend */ +#define EC_SUSPEND_L GPIO(KPROW1) +/* Cr50 interrupt */ +#define CR50_IRQ GPIO(EINT16) void setup_chromeos_gpios(void); |